CSSE3000/CSSE7001 - Digital System Design
Lectures, Tutorials and Lab Experiments
Timetable
(Lecture material will be updated and made available in good time before
lectures )
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Lectures Wednesday 2:00 – 3.50pm Room 47-104 |
Tutorials Wednesday 4.00-4.50 pm Room 47-104 |
Laboratory Friday 8.00-9.50am, 10.00-11.50am Room 47-104 |
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Week 1 |
2 Mar |
Subject Organisation Introduction to Modern Design Methodology Read Chapter 1 of your textbook for revision of required background material Below you find some additional material for revision: Minimisation of Combinational Circuits using K-maps,
Multi-output and Multilevel Synthesis - self reading |
2 Mar |
Revision of Background Material Optimisations with Boolean manipulation, K-map, multilevel and
multi-output functions |
2Mar |
Prac 1 -Introduction to XILINX FPGA design environment (revision) and testing in VHDL
Software download page (get Xilinx 11.4 and Digilent Adept, do not worry about active HDL) |
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Week 2 |
9 Mar |
Introduction to design with VHDL VHDL basics VHDL for synthesis (Lect 4) VHDL reference from the Brown/Vranesic textbook (vhdl) Read Chapter 2 and Chapter 6 of your textbook Roth, "Digital Systems Design Using Vhdl"
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9Mar |
VHDL and XILINX development system
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11 Mar |
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Week 3 |
16 Mar |
Arithmetic Circuits MSI combinational building blocks - self reading |
16 Mar |
Registers and Combinational circuits in VHDL Design with combinational blocks |
18 Mar |
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Week 4 |
23 Mar |
Design Example with FSM |
23 Mar |
VHDL design exercise |
25 Mar |
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Week 5 |
30 Mar |
Implementation
Technologies More about implementation technologies - self reading |
30 Mar |
FSM Design Practice Tute 4
Sequential logic design methods Tute 5
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1 Apr |
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Week 7 |
6 Apr |
Timing aspects of logic design |
6 Apr |
Sequential logic design methods Tute
5 |
8 April |
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Week 6 |
13 Apr |
Advanced design example with FSMs (Lect 11) |
13 Apr |
MID-SEMESTER EXAM State diagrams for practice - if you find transition conditions confusing, just fill in with your conditions. For your practice the complexity and structure of the state diagram is more important. Sample Exam Solutions you can guess the questions from these solutions, but you can bet this year the questions are different. It is a tiff file, open with Windows fax viewer or other Tiff viewers
FSM Sample Exam Solution - this year the FSM will have more complicated transitions. |
15Apr |
PROJECT 1 (cont.)
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Week 8 |
20 Apr |
TopDown Design from Behavioural
Description Self reading material below complements lecture 14 |
20 Apr |
Mid Sem Exam Results Top down digital design tute 6 |
22 Apr |
Public Holiday - No Classes |
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27 Apr |
27Apr |
Mid
Semester Break - no classes |
29 April |
Mid
Semester Break - no classes |
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Week 9 |
4 May |
Bus and memory Memory |
4 May |
Prac 6 - Introduction to System on chip Methodology
SELF STUDY ASSIGNMENT SPEC |
6 May |
PROJECT 1 (cont.) – Assessment week |
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Week 10 |
11 May |
Medium Scale Integration (MSI) Sequential Devices - self reading Basic computer structure - self reading |
11 May |
Top down digital design I tute 6
RESULTS: PRACS 1-6, PROJECT1, MID-SEM EXAM |
13 May |
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Week 11 |
18 May |
18 May |
Top down digital design (cont.) tute 6
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20 May |
PROJECT 2 (cont.) |
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Week 12 |
25 May |
Advanced timing issues |
25 May |
Design with memory modules tute 9 |
27 May |
PROJECT 2 (cont.) – Assessment Week |
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Week 13 |
1 Jun |
Miscellaneous advanced topics (lecture in development) |
1 Jun |
Design for testability |
3 Jun |
self study completion and presentations |