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 Feedback from System-on-Chip introduction Lecture (4th September 2006)

Most important point

  • Design of complex systems at transistor level is impossible (x2)
  • Modular level design
  • There are always tradeoffs involved with every design decision
  • SoC design techniques and issues (x2)
  • Types of different SoC in use (ARM, PowerPC, ...)
  • Different approaches to SoC implementation technologies (FPGA -> ASIC)
  • Point of (r)SoC is to enable building more complex systems, by re-using existing components (IP cores)

Least clear point

  • IP Cores
  • Concepts of component interconnects and bus interfaces
  • Clock management
  • Why (r)SoC is a necessity, not just something useful
    • It's all about designer productivity, which directly influences design cost, and therefor the economics of designing and fabricating complex digital systems.  While in principle it's possible to design an entire SoC at the transistor level, it would take so long, and be so difficult to verify and test, that the desing would probably be obsolete by the time it was completed.
  • Why digital logic and memories do not mix
    • Typically, embedding DRAM onto an SoC would typically require two passes through the fab (different processes)
      • Very expensive
      • Poor yield
    • Some recent articles about eDRAM (embedded DRAM)
      • NEC eDRAM claims to have solved the eDRAM process problem - 90nm DRAM on same CMOS process as SoC
        • Being used in Nintendo Wii gaming platform
      • EE Times article explaining in some detail about the issue, and approaches to the solution
    • In FPGAs - FPGA vendors are generally process technology leaders (first to 90nm, 65nm).  Memory CMOS processes (esp flash and  DRAM) typically lag by one or two generations (e.g. flash currently at 130nm).  So, putting Flash or DRAM on latest FPGAs would require either two fab runs, or hold them back at older CMOS technologies.

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