MGC Tute: Setup and Schematic Drawing

Mentor Graphics Tutorial 1: Creating Schematics in Design Architect

Throughout this tutorial, you will need to perform tasks using various menu and screens. You are asked to explore the program and search these options for yourself. If half the window is missing, try using the right mouse button, page up or page down keys, and the scroll bars.

Setup Tasks

Please refer to the lecturer/tutor's instruction to setup the environment for running Mentor at AMC.
You will be using ICFlow (since you are making an IC) and the ASIC design kit (ADK) for this tutorial.
For the purpose of this tutorial, create a directory called beginner in your home directory (Unix syntax: cd; mkdir -p beginner).
Make sure the environment variable $MGC_WD is set to your working directory, which is $HOME/beginner.
It is very important that you set the working directory correct every time you load a design.

Some material in the following tutorials are from David M. Zar (Washington University, St. Louis) and Mentor Grahpics Corporations.

Drawing a schematic using Design Architect

You need to start Design Architect on your workstation. Start Design Architect with command adk_daic. This will load Design Architect-IC with a special library available that contains all the parts you will need for automation of capturing your designs. Design Architect-IC is a customised version of Design Architect for creation of ICs.
Once Design Architect-IC is running, you can begin to design a 2-input NAND gate and a 2-input NOR gate. We will use a 2-input NAND gate as an example in this tutorial.
If your windows are drawn wrong for whatever reason, use menu MGC - Cleanup Windows or type in command "$cleanup_windows()" to refresh the screen. Or simply resize the window.
We will now step you through the process in creating a 2-input NAND gate. You should interact with adk_daic through the context sensitive palette on the right side of the window.
If you cannot see the palette as shown above, go to menu MGC > Setup > Session. Check the boxes with Show Palette and Show Softkey Area.
Open a NEW sheet by clicking on the Schematic button. Change the default name of the component from $MGC_WD to nand2. Click the Options... button and choose New Sheet. OK the default Schematic & Sheet names. Make sure the component is open as Editable.
Once a new empty sheet is open, take a look at the palette again. It now has different options. All menus and palettes in Mentor Graphics are context sensitive - the available option changes according to the activated window. The palettes all have differenct names at the top.
Click the ADK IC Library button to activate the ADK Library. (Normally one would start this program with da_ic, but we have obtained an ASIC Design Kit - ADK - which provides us with a customised library. adk_daic script activates this library at startup.)
If the menu does not fit into the screen, you need to activate the scroll bar by right-clicking the menu and choose Show Scrollbars.
As you probably know, a 2-input-nand gate will have a MosFET schematic similar to:
Now put the two n-type MosFET transistor as shown (click on nmos; if you want to cancel operation, use ESC key). They are four terminal FET devices, so you will need to make four connections later. I recommend to leave space between symbols, and then use wires to connect them up. This could save lots of check-warnings later.
Now investigate the select (F1), unselect (F2), delete (del), and undo (right-click) operations.
Using the same procedure, put two p-fet-4, port In (for 2 inputs, vdd and gnd) and port Out.
Wire up the components. Try (F3) or ('w' key), click to make turns and double-click to end. Take care between cross-overs or connected wires. Rename the net names on the three ports as shown (hint: the ports are part of the wire, so try selecting the wire and right-click on the wire...). The names cannot contain ",", otherwise the simulators you use later on will not work properly. The names on the pictures are A_nand2, B_nand2 and Y_nand2.
The transistor width and length can be changed to vary its resistance for symmetrical operations. Let assume that we want to build a higher drive gate, so we need to make the transistors wider. Make both p-fets 1.2u wide and the n-fets 0.42u wide. Make sure the length is set to minimum value 0.18u and don't change any other properties at this time. Hint: Select the transistor, right-click, choose Properties and expand the menu to see Modify Multiple, look for width or alternatively select the transistor and press ('q' key) to bring up the properties menu...
When you've finished editing the schematic, click the schematic button to return to the main palette.

You should now save the sheet. Before you do so, it is a good idea to check if your schematic contains any errors, eg. unconnected pins. Go to File Drop down menu and choose Check Schematics. A notepad screen will pop up.

A common mistake here is that you've only connected 3 terminals on your FETs. Even if you have no mistakes, deliberately delete a wire and check the schematic again. Make both your schematic window and the report window visible. Now if you click on the names on the instances/wires on the report, the corresponding parts in the schematic will be highlighted, making debugging easier.

The warning about Schematic is not registered with an interface is expected and will be rectified by generating a symbol for your schematic.

If you see warning such as: "Unable to evaluate property "awidth" on I$1, Unable to evaluate expression, Unable to resolve expression symbol lambda", don't panic, this is expected. The transistor you've drawn is based on the lambda rule, ie., the value of the width is resolved when you decide the value of lambda. This value is provided when you create a "viewpoint" for the schematic later, so it will not cause any problems for now. However, you must deal with any other warnings or errors.

Investigate the function Instance > Auto under Name part of the schematic palette (remember show scroll bars). All instances (such as transistors, wires, ports etc) of your schematic will have a name. This function will let you change the default name on the selected instance, making the report much easier to read. For now you should stay with the 'Auto' option, as the netlist generation is dependent on some aspects of the given instance name. When you are more familiar with netlisting, you can try the manual option.

Select any object and investigate the function of drop down menu Report -> selected object.

Make a symbol for your NAND gate

Use the drop down menu Miscellaneous->Generate Symbol menu item to automatically generate a symbol for you.
If you want to replace the old symbol, choose Yes on Replace existing. Change any of the options in the dialog box as needed. The default options are usually good. Click on the OK button to generate your symbol.
Your symbol will be a simple rectangle with three pins. This is fine although you could modify the body of the symbol to look like a typical NAND gate. Click on the Draw button and try the selections available.
We will place the name of the gate on the box to help us remember it in the future. To do this, use the Text button, under Add and click on Comment Text and use the name NAND2 as the text. Place this text in the symbol by clicking on location.
Now you should save the symbol.
Don't forget to check the symbol in similar ways to checking the schematics. You can ignore the warnings about the pins not being on the interface. If you have any other errors, however, you need to fix them before moving on.
Close the symbol window.

Test your abilities by creating the inverter gate shown below. Generate a symbol for it, too.

Let's review what was done...

We have started the process of Schematic Driven Layout to capture our IC designs in Design Architect-IC. You've used n-FETs and p-FETs from a special library provided by a particular ASIC vendor. These components have the necessary properties pre-assigned to them in order to drive the entire process. After placing these FETs, you wired them together and add ports and net names for identification.

Schematic Driven Layout (SDL) is one of many design processes you could use to create IC layouts. So far we have created the schematic of the logic we want to put on a layout. The information is contained in a logic database (as a schematic) and maintained by DA-IC. Later on, the layout will be generated based on this schematic.

You can use SDL process to place devices or library cells in a cell automatically or manually (interactively). SDL handles the cells, parameters, and interconnections automatically, but the designer creates the detailed final layout. This will be demonstrated in the later tutorials.

The database that this SDL procedure uses is called an EDDM design database (schematic). You use Design Architect to create the schematic using components previously defined for this purpose. Some examples of these pre-defined components are n-FETs and p-FETs, resistors, capacitors as well as power and ground connections.

SDL Requirements

Successful use of the SDL design flow requires a complete and stable logic database, and cells and/or device generators for each object in the schematic. The basic devices such as p-FETs and n-FETs, resistors and capacitors have been defined for you from the device generators. You can also use cells that you design in hierarchical design procedure later.

Schematics and Instances Properties

Schematic instance properties help drive device generators and filter functions by providing component information.

Pin Names

The schematic instance pin names, which are defined in Design Architect and added to the instance symbols, are used to define the connectivity in the layout. The pin names are required and should not be changed in Design Architect.

Schematic Instance Properties

An example of an instance property SDL-use is the property that contains the component type (Element property), which SDL uses to determine the name of the device generator. Other properties you can add to schematic instances could be useful to front-end designers, such as MOS gate length and width. Also, back-end designers might find it useful to have other properties added to schematic instances, such as contacts on source, drain, or both.

For example, the MOS device generator requires two properties, named "l" and "w", for width and length. It can also use many other properties, such as contact size and so on. Many of which have been set for you and you will not need to worry about them.

Last Modified: 03/08/2006 19:14.

Prepare by Simon Leung, leungks@itee.uq.edu.au