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Mentor Graphics Tutorial 2: Simulation of Schematics using ELDO and ADMS tools

Some material in the following tutorials are from David M. Zar (Washington University, St. Louis) and Mentor Graphics Corporation.

Creating the Test Bench for NAND gate.

Before you can simulate the 2-input NAND gate that you designed earlier, you need to create a test bench for it.  So open a new schematic and we will design the test bench there.

1. With adk_daic, create a new schematic and call it tb_nand2.
2. Now, we will insert your NAND gate first.  Under Add click on Instance. Choose nand2 and put it on the middle of the empty schematic.
3. In the ADK IC library menu, put in two PAT voltage sources to the two different inputs. 
4. In their properties, make sure vhi is 1.8V.  Change the pattern to 00111101 and 01011001 to test various combinations of inputs.
5. Set the rise time and fall time appropriately (for example 10ps). Set the desired width of the pulse.
6. Add a capacitor load to the output of NAND gate. Edit its properties and set capacitance value to 40fF.
7. We also need to supply 1.8V to VDD!  So put in a DC source and set it to 1.8V.
   
8. Save and check the schematics.

Simulating the test bench using ELDO^TM (or SPICE) Simulator.

For those who are familiar with SPICE, you will notice that design architect provides a graphical front-end to setup the SPICE simulation of the schematic. Eldo is Mentor Graphics software SPICE simulator. da_ic is used to generate SPICE commands for Eldo interactively.

The SPICE model for the transistor is obtained from ASIC foundries.  The ones we are using came from www.mosis.org. The complete model is a BSIM3v3.1 model at level 49 (the model file shows level 53 because Eldo level 53 = Berkeley level 49) and the simple model is level 3.  Each time a new wafer is made, the SPICE model for the transistor is different.  So for accurate simulation, always obtain the model from the foundry you will be using.

We will carry out a full SPICE analog simulation of the test bench.

1. Open the test bench.
2. Click on Simulation on the schematic edit palette.
3. The palette title should now be schematic sim and the colour of the window of your schematic is green.
4. We will need to perform setup for the simulator.  Note that these setup options are saved in the tsmc018a viewpoint (more about viewpoint in later tutorial). As long as the viewpoint is not deleted, the options are saved.
5. Choose Session - simulator/viewer. Choose Eldo as the simulator and EZwave as the viewer.
6. Choose Session - Netlister. Enter GND as Set Node 0. (The ground symbol used in ADK is shorthand to GND. If a different ground symbol is used, enter the corresponding ground reference name here.)
7. At this stage, take a look at the message at the bottom of the window. There should be no errors. The commands are written to a .cir file as you set up the simulator.
8. Choose Lib/Temp/Inc - Libraries, in the library path click Browse and navigate to $ADK/technology/ic/models/.  Choose tsmc018.mod for a transistor model based on TSMC018 technology.
9. Choose Analyses, and select Transient and click on Setup.  Make Stop time 1500N (i.e., 1500ns).
10. Select one of the inputs. Click on Probes/Plots, choose Save Selected... and make sure Voltage is selected. Click on Advanced and check the correct analysis type (tran) and choose a Magnitude plot.
11. Repeat this process individually for any nets/inputs/outputs that you want to plot.
12. If you choose all the nets/inputs/outputs simultaneously, all the waveform will be combined into the same graph. In EZwave, Right-Click on the waveform window and choose Split to make them individual again.
13. Choose Run ELDO to perform the simulation.
14. Choose ASCII Files -  view log. The log file should report no errors or warnings.
15. Choose View Waves. Make sure you activate the schematic window or the option will not be present. A new window will come up.
16. Sometimes (if step 12, 13 and 14 are not followed), you will now need to select the voltages you want to see: in this case, we want to examine the inputs A_in & B_in as well as output Y_out. So double-click on V(A_in), V(B_in) and V(Y_out) to view the waves in another part of the window.
17. You will now see a graph with all three voltages waveform all overlapped on each other.  That's ok, we can fix it. Click anywhere within the plot area. Now the "Graph" menu is activated, select it and choose split. Now the waveforms are separated.
18. They can be re-combined: choose a graph, now go to Graph - include, now click on another graph that you want to add to. Similarly you can remove any graph you don't want.
19. Click End Sim to save the simulation setup and end the simulation.

You should check your inverter to ensure it works as expected.As an exercise create schematics for NOR gate, AND gate and OR gate.

Advance simulation exercise

Now lets end the current simulation. We will insert a capacitor at the output to see how it affects the output waveform. Click on End Sim to bring up the Schematic Edit palette so that we can add the capacitor in the ADK library to the schematic. Make the capacitor 40fF.

Now go back to simulation and shorten the time of simulation to say, 500N to see the rise/fall time of the waveform. Investigate the correlations between the load, the length and the width of the transistors.

Simulating the test bench using ADMS tool

The Mentor Graphics ADVance MS (ADMS) tool is a single-kernel, language independent functional verification environment for digital, analog, mixed-signal and RF circuits. This platform is built upon four high-performance simulation technologies: Eldo(tm) for analog, ModelSim(r) for digital, Mach for transistor-level and Eldo-RF for Radio Frequency simulations.

1. Close the all Design Architect windows.
2. Before using the ADMS simulator, we must create a library (lets call it myadms_lib). From the Unix command line type the following command valib myadms_lib.
3. This command creates an ADVance MS library called myadms_lib. It also creates a ModelSim library within this library. Observe the progress messages as the various steps in creating the library are executed. You should find two files (adms.ini & modelsim.ini) and a folder (myadms_lib) in your working directory.
4. Now define this library as the working library using vasetlib command. From the Unix command line type the following command vasetlib myadms_lib. You will see the .ini files are updated accordingly.
5. Now open the test bench using adk_daic.
6. Click on Simulation on the schematic edit palette.
7. The palette title should now be schematic sim and the colour of the window of your schematic is green.
8. Choose Session - simulator/viewer. Choose ADMS as the simulator and EZwave as the viewer. The simulation palette should now have Run ADMS button instead of the Run ELDO.
9. Follow steps 6 to 12 from the previous section.
10. Click on Run ADMS to invoke the simulation.
11. Choose View Waves to invoke EZwave to view the waveforms and Click End Sim to end the simulation.

Create schematics for NOR gate and appropriately size the transistors. Test the gate and ensure it works as expected.

Hierarchical Design and Simulation

In this tutorial, we will use the skills learnt so far to perform a hierarchical design of a 2-input exclusive-or gate (XOR) and construct a 2-bit full adder, which can be built from the gates you have designed earlier.

1. Create an XOR gate as suggested in the figure, using NAND gate and Inverter using the Add Instance feature. This is one way of obtaining the XOR gate but not the best way. Are there better ones than this design ?
2. Create symbol for the XOR gate.
3. Check and save the Schematics and the Symbol in your working directory.

   

Use the gates you have designed and construct a 2-bit adder block.Create a Symbol for your two bit adder. Check and save the Schematics and the Symbol. Make sure each time you design the schematics, you have separate pins for VDD and GND.

Now lets create a testbench and simulate the two-bit adder you just designed

1. create a new testbench schematic for two bit adder.
2. Use the PAT sources to define all possible combination of inputs(32). Let the bit width be 5ns with 10ps rise and Fall time.
3. Check and save the schematic.
4. Prepare your design for Simulation using ELDO.
5. Run the Simulation and ensure the Adder works as expected.
6. Lets Probe the ripple carry signal under the full adder block. Click on the Adder Symbol to select it.
7. Click on File->Open Down. A new window pops up with the schematics under the Adder symbol. Alternatively Hold down the middle mouse button while the mouse is over the symbol. Drag vertically down to make a RED vertical stroke. This will also bring up the schematic window.
8. Click on the signal you want to probe to select it.
9. Click on Probes/Plots and choose Save Selected. You will have Four options to choose. Choose Current/Voltage option and click OK.
10. Click on Probes/Plots and choose Edit this time. A window pops up showing the signals you have selected to view using EZwave.
11. Click on Current option, Disable the plot and Click OK.
12. Now Run the simulation and make sure the signal probed is as expected.

 Last Modified: 13 August, 2006 16:05:35.

Prepared by Simon Leung, leungks@itee.uq.edu.au

Modified by Balavelan Thanigaivelan, velan@itee.uq.edu.au

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