SDL on Silicon using IC Station

Mentor Graphics Tutorial 4: Schematic Driven Layout using IC Station

Some material in the following tutorials are from David M. Zar (Washington University, St. Louis) and Mentor Graphics Corporation.

Requirement

To perform this tutorial, you must have created schematics of your circuit using Design Architect.

We will perform an SDL layout of the nand2 cells created in previous tutorials, assuming that all errors and warnings are fixed.

The simulations must also show correct behaviour before attempting this tutorial - otherwise, you will end up with an incorrect layout!

If you have log out from your previous session, or performed other exercises/work, make sure you set the working directory to the one with your nand2 design.

Design Preparation

So far you have created a couple of designs (using Design Architect-IC) on your working directory. Well, you will probably want to do many different things to your designs, such as simulations, synthesis, back-annotation, or just simply putting different parameters into your design to see how the output changes. However, you don't want to alter your original designs. This is where "design viewpoints" is introduced.

A "viewpoint" can be conceptually seen as a "projected image" of your design. Think of an image projector, where the film is the source of your design. Then the image you see on the screen/board is the viewpoint. Now if you draw on the board, you can "modify" your design and see how the added information can impact on your design, but without "wrecking" your original design.

So a viewpoint allows other tools to work with your design. These tools can store data, or do whatever it needs on your viewpoint, all without changing your original. Of course, if you create more than one viewpoint, other people and other tools can work with your design without any problems. So each tool will need different parameters added to their viewpoints of your design. The MGC tool to create viewpoints is called dve or dve_ic, design viewpoint editor. As you can see, the more complex the program, the more parameters it will need.

Before you can build the layout of the design prepared in Design Architect, and any other additional tasks, you need to run the prepare for layout script. This script will create "viewpoints" for your use with the other tools. Click on prepare for layout in adk_daic to make the necessary viewpoints.

The following viewpoints and files are then created inside the subdirectory nand2:

eldonet	for use with Eldo Spice simulator
lvs	for use with IC Station when performing LVS of your design
sdl	for use with IC Station when doing SDL place and route
<design>.src.net	A Netlist file for your circuit required by the LVS tool

You should also run this option on the inverter that you designed.

The prepare for layout script will create these viewpoints needed for layout and verification. You only have to do this once per design. Even if you make changes to your design, you don't have to do this again.

If, for some reasons, your viewpoints are corrupted, or some unknown error occurs, it is worthwhile to try to delete the viewpoints and re-run the script. Activate design manager (dmgr or dmgr_ic) on your working directory, descend into your design directory (e.g. double click the folder nand2), delete the folders marked with with 'dvpt' and 'ba' on the icons. You will lose any settings made in the viewpoint (such as your simulation parameters).

Note: When you simulated your design, the simulator automatically prepared a viewpoint for you to contain all the simulation parameters. Since we were using TSMC018 technology, the viewpoint was called tsmc018a. All the setup information you put in were stored in this viewpoint.

Schematic Driven Layout using IC Station

Start IC Station with command "adk_ic &" on your working directory.
If your windows are not drawn correctly, use menu MGC - Cleanup Windows, type in command "$cleanup_windows()" or resize the window to refresh the screen.
Now you can create a new cell. Since the cell you are creating is a gate which can be used as a standard cell, Click on the palette on the right side Cell->Create or use menu File->Cell->Create.
For the cell name enter nand2. If you wish to store your layout files in a specific folder, you must enter the correct path. Select With Connectivity. Now enter the schematic viewpoint. You can use the navigator button or specify the path yourself. Select the sdl viewpoint inside the <nand2> design directory. The sdl viewpoint was created (by the script) to contain information needed for schematic driven layout, which is what we are doing. Be sure that you click on Logic Loading Options and set the hierarchy to Flat. Make the Angle Mode to all.
For the Process browse to the folder $ADK/technology/ic/process and choose the tsmc018 process.
For the Rules File, again browse to the folder $ADK/technology/ic/process and choose tsmc018.rules File. Click OK to accept the options you have set now.
At this point you could adjust the window attributes and set up the environment to suit yourself. Use the Setup->Session menu, and try out the different window layout and other session properties.
Once the empty cell has been opened, you should go to the DLA Layout menu via the palette menu. This will bring up the palette menu which has the most functions for doing your SDL design.
The top of the menu has two options for moving to other palettes: Device and Top. Device takes you back to the DLA Device palette and Top takes you back to the top IC palette where you came from. Try it out and then come back to the DLA layout palette.

A few explanations:

The Logic section of the palette has functions for setting the viewpoint of the logic source, closing the schematic view and updating the EDDM database if changes are made while the viewpoint is open. The Open menu item will open the selected logic source window. The Place section has functions for selecting instances and ports.

The Place section has functions for selecting instances and ports. The Inst item lets you place your instances from your schematic into your layout. The AutoInst item will automatically place all unplaced or selected instances into your layout. Port will place ports from your schematic into your layout.

Let's get back to work. From the DLA Layout menu, you need to open your schematic. Click on the Open button to see it. The new window could be hiding behind your current one.
Now you can place the devices into your cell. For this exercise, you will use the automatic placement method. Click on AutoInst on the palette menu.
The tools will locate devices that are of the same type and have connectivity such that diffusion regions may be shared. The cell will be automatically generated based on the length and width parameters specified on the instances.
The first thing you should do is zoom out to see all of your devices (select the cell window and try view menu. Overflow lines (in yellow) will show you the connectivity points you need to draw on your circuit. As you wire the circuit together, these overflows will disappear when you have made the correct connections.
You will want to spread out the transistors a little for the connections. The placement algorithm makes things fairly tight and you can always compact the design later. So click and drag a window covering the pmos transistors, to select them. Using the move option (from palette or Right Click menu), give some space between the two transistors. Now let's take a peek at the product you have finished so far.
Put the two windows side by side, both visible on the screen. Notice that when you select a device or a new object on the layout window, it is also selected in the schematic window. This cross-selection is very useful. Play around by selecting various objects and groups of objects to see how the transistors are constructed in the layout. Take note on the location of the channels, gates and connections.

Let's wire up the device. There are many methods for accomplishing this task. We will try out a few different methods.

Method 1:

The first method is very useful for wiring metal together. You can use AddR on the palette menu (within ADK Edit Palette). This will prompt you for a starting and ending point of a route. Make the starting point on the metal contact between the two PMOS FETS. Notice how, to the right of the pointer, it says M1. This shows that you are on routing layer 1 (or metal 1). Once you have selected the starting point for the route, a guide will appear showing you the clearance where you can place the route without any problems. Draw the metal path leaving a knee-bend as shown in the figure below by simply clicking at each corner. This will allow room for adding ports later. Notice how it is automatically drawn at the routing width specified in the processes file. Click on the pin on the N-FET to complete the route.

Method 2:

Another method is placing paths. You will place some polysilicon using this method since you cannot place routes in poly. (Only routing layers are useful for the AddR command and poly is not a routing layer.) First, show the layer palette to make things easier. To do this, type sho la p (this stands for "show layer palette" but is easier to type - try to find the menu option for this command as well). Now, while holding down the control key, click on the layers POLY and METAL1. If you need to scroll down the window, release the control key before scrolling, then hold it down again when clicking on the layers.

Now click on Path. You will be prompted for a location. Before placing the path, click on the Options button on the prompt bar. Choose the layer name in the dialog box, or click on the poly layer in the layer palette at the top-right corner of the window after you have specify the width. You need to change the width to 2 lambda , but leave everything else alone. Select the Keep Option Settings box and exit the dialog box. Now you are ready to place a route on the poly layer. Wire up the gate inputs with poly. When you have made a complete connection, the overflow line will disappear. Be sure to follow the design rules! (Two lambda minimum width). If you need to use metal, then you can simply click on the metal layer in the layer palette (or on the contact to place a contact). Remember to change the width as needed. Be sure to wire all the overflows.

Once you have the gates wired together, you need to place the ports for the inputs and outputs. Before you can place ports, you have to select the type of port you wish to use. Go to the Setup->SDL pull-down menu. Click on SDL Port Styles and then press the Setup button. You should then select Process Port on the dialog box to display the ports defined for this process. We will put our I/O ports on metal 2, so select the default line and then click on Preview to see its parameters. Notice that it is on metal 2 and it is 5x5 lambda. Click OK to select this as the default port style.
To place the ports, select the two inputs and the output in your schematic window. Then make the layout window active, again, and click on Port in the DLA Layout palette menu. You are prompted to put these ports one by one. The net for the current port to be placed is highlighted in the layout window. This makes it easier to see which port is being placed. Place the ports near half way between the two FETS. Note that the ports are not yet connected to the transistors. For future routing purpose, put the I/O ports near the middle of the cell, but not necessary align next to each other, allowing some room for routing later.
What about the power ports? You have VDD and GND, as well. These ports should not be placed on metal2, as they should run on metal1. You need to place the ports like the inputs and outputs, then you have to change the port to metal1 and also resize the port to make it the size you want (all ports are 5x5 lambda by default). So similar to previous step, put the VDD port above the PMOS and GND port below the NMOS. Select the port, use Objects - Change - Layer to make it metal 1. Make sure you resize the ports to desired size.
Now that you have the VDD and GND ports placed, you should see overflows going to them from your transistor devices. You should wire up the power and ground connections from the devices.

Now wire up the other ports. Since the signal ports are on metal2, you will need to get from poly to metal1 and then to metal2 and for the input. You'll have to go from metal1 to metal2 for the output. There are some handy commands that have been scripted to help you do this. Simply place the poly contacts and vias as you need (see figure) and then wire everything up using any method you choose.

In order to place a via from metal1 to metal2:

Simply type pp. This is the "Place Port Via" command will get a metal1-metal2 via for you. Now Zoom-in and select the Via and right click to select Edit -> flatten.

Alternatively, Click Via -> Active Via in the Edit menu of the DLA Layout palette. Choose the first option, which says "via".

In order to place a poly to metal1 contact:

The Poly Contact command pc will place a poly contact with metal1 centred at the mouse cursor. So be careful to point the mouse cursor to the place you want to place this contact. In case you want to move it, then select the whole contact. Press Ctrl-Left Mouse Button on the selected object and drag to move it to desired location.

Notice there are still two overflow lines? You will place diffusion contacts to bias the wells. There are two macros for these, as well. nwc: N-Well Contact command will give you a n-well contact. pwc: P-Well Contact command will give you a p-well contact. You should place an n-well contact on the VDD rail so that the contact's top edge is coincident with the top edge of the VDD rail. The p-well contact should be placed on the Ground rail so that it's bottom edge is coincident with the bottom edge of the rail, see figure for more details. The overflow lines will disappear once the contacts are "flattened". The contacts are blocks constructed and protected, and will not be recognised by the connectivity checker until it is told. So once you are happy with the position of the contacts, select it and right click, choose Edit - Flatten:, accept the default options. The overflow line will disappear.
Now it is time to see if you pass DRC. Use the DLA Layout palette Drc - Check. Simply click OK on the prompt bar and DRC will be performed. If Total Results is NOT zero, then you have violated some design rules. You should fix all DRC errors before you can move on with your design. Use Drc - First or Next to see where you went wrong. The text on the bottom of the page will give you some hint of the rules you have broken.

Finally, you should place metal1 blockages over all the metal1 in your cell. The reason is that, by default, everything but the ports are invisible at upper layers of the hierarchy. If we use this cell to make a larger cell, we don't want to route metal1 over our metal1 wires in this cell! The ADK provides a script that will do this for you automatically. Simply type ab1 in the layout window and all your metal1 shapes will then include metal1 blockages over it. Should you ever want to remove these (to make editing easier, for example), simply remove the blockage with the rab1 script. Note that metal1 blockage is essential to later tutorials, but makes editing the cell very difficult without removing it first.

Now perform the procedure above for your NOR and Inverter gates you designed earlier. Here is a figure of Inverter Layout to help you along. You should put the power and ground ports in the same place on all cells as this makes routing easier when many cells are combined to form a complex function. Remember to make all the standard cells you create are of same height from VDD to GND.

Last Modified: 14 August, 2006 09:58:22.

Prepared by Simon Leung, leungks@itee.uq.edu.au

Modified by Balavelan Thanigaivelan, velan@itee.uq.edu.au