Advanced Layout Techniques

Mentor Graphics Tutorial 5: Advanced Layout Techniques

Some material in the following tutorials are from David M. Zar (Washington University, St. Louis) and Mentor Graphics Corporation.

Design assumption

This tutorial assumes that you have a design layout produced similar to the one in Tutorial 4.

We will describe the procedure using our nand2 example.

What's a good layout?

Although there is no universal answers, there are of course some rules which can be followed to obtain a good layout. In essence, you want to be able to reuse your layout as part of a bigger design. If your layout can be reused easily, then the layout is good. There are several aspects to this goodness of which some are listed here:

Cells have uniform height (aspect height) so that they will line up in rows during automated placement. Power and ground rails will then also line up. So no matter how many cells you have in a big layout, they will all align with no DRC errors.
Cells have uniform rules for placement and types of ports. A port is an input or output of a cell. For example, a 2-input NAND gate has three ports: A_nand2, B_nand2, and Y_nand2 where A_nand2 and B_nand2 are the two input ports, and Y_nand2 is the output port. The significance of a port is that during routing, only ports may have wires between them. Generally VDD and GND are considered to be port of type IN, although some designers treat them as INOUT type. (use of global for VDD and GND are usually avoided)
Cells should have relatively low delay. Delay is largely controlled by transistor sizing, length of connections and wiring capacitance (routing). The size of the transistor has been designed at the schematic level so routing is of primary concern during layout. It is desirable to keep all routes short and keep the use of vias and contacts to a minimum. It is also important to minimize the poly routing length. Wider tracks lower the resistance but increases the capacitance. Within a cell it is good practice to use only poly and METAL1 for routing.
Cells should have low input loading. This is achieved by minimizing the input capacitances which is done by keeping the input wiring to a minimum (also helps delay!).
Cells should have high output drive. This is achieved by minimizing the output capacitances which is done by keeping the output wiring to a minimum (also, again, helping delay). Of course the output drive is also determined by the output transistors.
It is obvious that it is desirable to reduce the total amount of wiring (poly or metal) needed in the cell.

In order to satisfy design rules and make the cells routable, there are other considerations in the cell design:

Power and ground rails are placed at the top and bottom of the cells and must be extended to the full width of the cell (in fact, the width of the power and ground rails defines the width of the cell).
n- and p-wells (or called tub-ties) are placed across the full width of the cell adjacent to the power and ground rails. This also simplifies transistor placement and allows for the cells to be abutted with little effort.
All ports will be at least 2 lambda from the edges of the cells. This allows for all design rule constraints between contacts and metal layers to be met at the cell level and for routing.
Metal3 blockages, of size 2x2 lambda, must be placed over each via to keep via2 from being placed directly over via1. This includes all ports as well as internal vias. Luckily, when placing a port with the "pp" command, this is done for you.
An fp1 layer will be placed around the entire extent of the cell for auto-placement purposes.

The good news is that a lot of these rules have been incorporated into some handy commands that you can use to help automate the layout of the cells. You have met some of these commands before. Many of these rules are not checked in an automated fashion so be sure to at least glance at your cells and check them.

Some useful tips on using IC Station

We assume that you have explored IC Station well enough during the previous tutorials. The tips presented here will help you speed up the layout process and use IC Station with ease.

Setting up the IC Station environment:

Open IC Station in your working directory. Click MGC on the top left menu and choose Setup... option.
This will bring up a popup menu. Click to tick the Show Softkeys box and Click OK.
The Softkeys box appears at the bottom of the IC station window. Remember that 'F2' function key is very frequently used to unselect ALL in the layout or schematics window.
If you haven't set the Selection Filter appropriately, you must be experiencing some difficulties in selecting various layers. So Open your nand2 cell for editing your layout. Choose DLA layout palette in the IC palettes. Click logic -> Open the schematics.
Click on the layout window to make it active. Choose Setup drop down menu on the top and click on the Session... option. Choose Left Right Tiling as your window layout in the pop menu.
The windows will now be tiled appropriately. Now choose Setup again and Click on Select Filter this time.

Make sure the Inside option is ticked and Outside option not ticked in the Area Relationship box. In the Point Select Target box choose the In Closest option. Choose No in the Intersect box. Choose the Auto Select ON option. Click OK to accept these options. Lets review the changes that will result in choosing these options.

Point Select Target In Closest	This option specifies the action taken when the Select > Select > Area menu item is executed with a POINT supplied as its argument. The CLOSEST object surrounding the Selection Point is selected.
Intersect	Specifies whether intersecting objects are to be selected.
Area Relationship Inside	Selectable objects totally contained within the area are selected. Coincident points and edges are considered in.

Once the Selection Filter is set, it becomes easy and flexible in choosing various objects in the layout window most of the time.

Now Click Setup once again, and choose Dynamics... option. In the popup window, Choose Crosshair Style to be Full 90 or Full 45 which ever you prefer. Choose Crosshair Target as Square with Radius 0.5. Set OTF Drc Parameters to Highlight Only and Highlight Attributes to Use DRC Layer. Make sure Redraw Level is set to ALL, Auto Popup Info to Full Hierarchy and Drag Complexity = 100. Click OK to accept these options.

Lets review the use of these option settings.

Crosshair Parameters	These Parameters give you different Crosshair Styles which will guide you draw long paths in straight lines.
OTF Drc Parameters	Specifies whether or not to apply the DRC spacing rule checks when moving, copying or placing an object or a group of objects. Our setting HIGHLIGHTS the areas when the spacing rule is violated!

Our environment options are standard ones and very useful most of the times when drawing a layout. So make sure these options are set, when you start IC station.

Lets explore some of the editing tips which will be useful most of the time during editing your layout.

Modifying the Centreline:

You can change the shape of a selected path or device to extend the endpoints of an existing path. You can also add or move vertices to a path or device defined by a centreline. The following figure is an example of modifying the centreline:

Extending the Centreline of a Path

Select the path that you wish to extend.
Right Click to bring up the menu and Choose the Edit > Modify Ctrline menu item.
Position the cursor at the point on the centreline that you want to extend. Click the Select button.
Move the cursor to the desired point for the centreline and double-click the Select button. The path is extended according to the new centreline.

Changing the Direction of a Path Centreline

Select the path that you want to modify.
Right Click to bring up the menu and Choose the Edit > Modify Ctrline menu item.
Position the cursor at the point on the centreline that you want to modify. Click the Select button.
Move the cursor to the next point for the new centreline and click the Select button.
Continue entering new centreline segments until all modifications have been made. If you make a mistake, you can remove the last segment with the Backspace key.
Position the cursor on the last point of the new centreline and double-click the Select button. The path is modified according to the new centreline.

If you select Auto Complete Outlines in the Setup IC Dynamics dialog box, every time you click the select button to establish a vertex for the modified centerline, the complete outline of the path will be drawn from that point to the initial vertex.

Moving the edges:

This task has been already covered in the previous tutorial and has been presented here again, as a reminder. You can move selected objects to a specific location. For each edge that you have selected, you are prompted with an image of that edge you can position where you want the edge moved to. You can move multiple edges by selecting more than one edge before performing the move. The following figure contains examples of moving a single edge and multiple edges:

Press the Unselect All function key.
Position the cursor at a point near the edge you want to select.
Click the Ctrl-Select button. The nearest edge is selected.
If desired, select another edge by clicking the Ctrl-Select button. The nearest edge is also selected.
Press and hold the Ctrl-Select button.
Drag the ghost image of the edge to the desired location. As you move the edge, the cursor readout provides a location reference.
Release the Ctrl-Select button to move the selected edge. The moved edge remains selected.

If you select Auto Complete Outlines in the Setup IC Dynamics dialog box, the complete polygon or path automatically adjust its size to the current location of the cursor.

Improving your Layout

Let's improve on your last design, nand2.

Open your nand2 layout for editing.
Locate the co-ordinates 0,0. If your design is within the rectangle defined by the co-ordinates (0,0) and (25, 120), move it outside this area.
Enter command pr. This is a macro that places VDD, GND and the required well geometries to help guide you and to assure the cells are all properly defined in height (120 lambda) and have the necessary power/ground ports. If you click on the top metal layer in the layout, you will see in the prompt bar that it is part of the VDD net. Likewise, selecting the lower port will show it's on the GND net. Got it? Top is VDD, bottom is GND... just like in the schematic.
The macro also pre-define the n and p well. You don't need them as the transistors already have them. So they can be deleted if there is not enough space. Otherwise, the space they occupy can be used for routing. 120 lambda is the size that all ADK cells are designed to - you can choose your own size if you want.
Now move the transistors to near the new power rails.
The transistors appear to be overlapped. However, if you only select the poly on one of the transistors and choose move, you can see that they can be separated. In larger design you may not be happy on the automatic generation of the transistors. You can manually select and move them around and re-merge them to the positions that you want. Try it out! Don't forget the yellow overflow lines, they will tell you which part of the transistor is connecting to the next transistors. You can also flip and rotate the transistors if needed.
You will see new overflows warning you that the connectivity is broken by the movement. That's ok, as we will fix them soon.
The width of the "new" power and ground rail is definitely too narrow for just about any cell, so select them individually and stretch them to the right width. Both rail must be of the same width.
Do you notice that each of the rail is made up of two objects - one METAL# layer and the other METAL.PORT# layer? Well, the metal layer ensures the region is filled with metal, and the METAL.PORT# layer is to tell the others accessing the cell that it is a port (power or signal). when you reuse the cell, you know that any region marked "port" needs external connections.
Now you can delete the "old" power and ground rails.
Fix up the rest of the cell by moving and resizing the remaining objects. Don't forget the good layout guides!
It is advisable to only use metal1 within the cell. This way, you can use METAL2 to perform routing between cells without worrying about the internals of each cell.
A word about the well contacts: you should place a well contact for every power/ground connection and as close to them as possible. You should also have one for about every 5-8 transistors. We'll place two of each in this case, for good measure. Do not place them within 2 lambda of the cell edge. You can never have too many well contacts (or tub-ties) so you should put as many of them as allowed.
Don't forget: extra metal add much less capacitance than extra poly does! Minimize poly lengths!
Run DRC to make sure you did not violate any design rules.
Once you are satisfied with the layout, don't forget to run ab1 script for Metal 1 blockage.
You will also need to add a floorplan shape (fp1) so the floor-planner knows how big the cell is. The fp1 shape should enclose the full extent of your cell. There is a macro pfp you can run that will do this for you.

At any time you wish to add comment to the layout, you can do so by selecting the Comment layer (show layer palette) and selecting Text under the Add Objects on the Easy Edit menu palette.

If you want to insert a layout you have created earlier, or another complete layout, use Cell under Easy Edit palette. However, this option (if used incorrectly) can easy introduce error when you check your layout against your schematics. Use with caution.

Improve on your inverter design, too.

Last Modified: 18 August, 2006 16:06:29.

Prepared by Simon Leung, leungks@itee.uq.edu.au

Modified by Balavelan Thanigaivelan, velan@itee.uq.edu.au