LVS and Post Layout Simulation

Mentor Graphics Tutorial 6: Layout Verification and Post Layout Simulation

Some material in the following tutorials are from David M. Zar (Washington University, St. Louis) and Mentor Graphics Corporation.

Design assumption

This tutorial assumes that you have a design layout produced with schematics. This layout must have passed all the design rule checks without any errors and preferably without any warnings. See previous tutorials for procedures to get such designs.

We will describe the procedure using our nand2 example, created in the earlier tutorials.

Design Preparation

Before you can carry out the LVS and extraction procedure, you will need to prepare your layout. Go into adk_ic (layout editing) and bring up your layout. Select Connectivity -> Port -> Add Text On Ports: from the drop-down menu. Enter METAL1 for the Shape layer and METAL1.PORT for the Text layer, and in the new box which comes up, enterMETAL2 and METAL2.PORT as well, and then click OK. This will automatically add text to all the ports in your design. Save your design.

Verification procedure: Layout versus Schematics (LVS)

During the layout procedure, you have specified lots of information about your design in IC Station either manually or automatically. It is quite possible that you have missed some I/O ports, overflow or routes. For consistency, the objects in the layout must match your schematic - no more and no less. In Mentor Graphics, Calibre will check this for you. In fact, the various extraction functions (which you will learn later) will run LVS prior to extracting to get required information. So it is important to find and correct errors now before carrying out any other procedures on your design.

In short, LVS checks the layout against the schematic to ensure that they are equivalent.

From the menu bar select Calibre -> Run LVS. This will launch Calibre Interactive – LVS.
In the Dialog box that appears change the environment variable to $MGC_CAL. Click OK to start Calibre LVS.
If this is the first time you have run Calibre LVS, there will not be any available "runsets", so just click Cancel. If you have already created a runset (from a previous attempt), then use it to save you some time.
The Calibre Interactive GUI has 3 main parts: a menu bar at the top, a button palette on the left and the display area. The display area will change based on the current selection in the button palette. You should notice some of the buttons will be highlighted red, this indicates settings which have not been set correctly. Begin by clicking the Rules button on the left.

You should see two fields in the display area one for the rules file and one for the working directory. Set the rules file to: $ADK/technology/ic/process/tsmc018.calibre.rules The Rules button should now be green.
Next click the Inputs button. This panel controls the input files which Calibre will be using. Notice that there are 3 tabs: Layout, Netlist, and H-Cells, for the SDL flow we can ignore the H-Cells tab. The Layout tab should be set up correctly by default.
Click Netlist. This tab tells Calibre where to get the source netlist for comparison. You should already have an up-to-date netlist in your component directory. Click … and browse to find the source netlist, named <design>.src.net.
Now select Setup -> LVS Options from the menu. There are a large number of options available but for our purposes we are only interested in the Supply and Gates tabs. Under the Supply tab set: Power nets: VDD; Ground nets: GND.
Under the Gates tab you can set whether or not Calibre will recognize logic gates. If your design is just logic gates then leaving Recognize all gates or Recognize simple gates on should not be a problem. For analog or mixed-signal designs you should choose Turn gate recognition off to ensure that your design is truly correct.
Select File -> Save Runset As… and save the runset you have created. This will save you from having to set this up again. In fact, you can use the runset to perform an LVS check on any design by simply changing the Rule File and Netlist as needed.
You should now be all set to perform an LVS check. Click Run LVS. If a pop up asks to overwrite the layout file click OK to ensure Calibre sees any recent changes to your layout.
When Calibre has completed the LVS check you should see two new windows. One has the text LVS Report File and the other is Calibre – LVS RVE. If you passed the LVS check, the Report file should contain a check mark and a smiley face. Calibre – LVS RVE allows you to browse through any errors which have been found and highlight them in IC Station. If you do highlight any errors be sure to click the eraser button in the icon palette at the top to remove the highlighting before you quit RVE. Otherwise the highlights will stay until you launch RVE again and erase them.

My layout has some errors and warnings! Well, it happens. So lets fix it. Believe it or not, the best way to fix any errors is to read the report carefully! Use the coordinates given in your report to locate the suspecting errors. Here are some common errors and warnings:

Missing ports: you may have forgotten to tell IC station that polygon in your layout is meant to be a port. Well, try this: Select the polygon in your layout. With the shape selected, use the Objects->Make->Port: menu to make this a port. You will be prompted for the type (make it power) and for the port name. Choose the direction in or out accordingly (Power ports, VDD and GND, are always in).
Warning: Short circuit - Different names on one net. Well, check to see if those are meant to be the same net (i.e.. connected together). If so, rename the shape with the same name so it is consistent. This occurs most often at the ports - you may have placed the ports in the wrong order during layout. You can rename the port to the name of the connecting net to rid this warning, or delete the ports and add them back in correct order. Check to see if the action taken by the tool is what you want, eg. assigning the name correctly.
Read through the report! It has very important information about your design that you may not even be aware of!

Perform LVS on your inverter.

Extracting the Post-Layout Netlist

Now that you have completed your layout and confirmed it is correct, it is time to extract the layout netlist. This will give you a spice netlist of your layout complete with resistance, parasitic capacitance and coupling capacitance. For the extraction process you will use Calibre Interactive – PEX (Parasitic Extraction).

In IC Stations menu bar, select Calibre -> Run PEX. This will launch Calibre Interactive – PEX.
As with Calibre Interactive – LVS, if this is your first time running Calibre Interactive – PEX you will need to create a new runset, so just click Cancel.

Begin by clicking the Rules button and setting the rule file and working directory. The rule file should be of the form: $ADK/technology/ic/process/tsmc018.calibre.rules The Rules button should now be green.
Next click the Inputs button. The Layout tab should be set correctly and you can ignore the H-Cells tab. In the Netlist tab, set the source file to the same one you used for performing the LVS check.
Now select the Outputs button. At the top, the Extraction Type should be Transistor Level and you can choose one of the following types:
1. RCC – Distributed RC network with coupling capacitors
2. RC – Distributed RC network without coupling capacitors
3. C – Lumped net capacitance with coupling capacitors
In the Netlist, tab you can setup the output format and file name. For our purposes choose ELDO as the Format and Use Names From: Source.
Next choose Setup -> PEX Options from the menu bar. In the Netlist tab click the Ground node name: check box and enter GND. In the LVS Options tab set Recognize gates: to the same setting you used for the LVS check. Also enter the following: Power nets: VDD; Ground nets: GND.
Select File -> Save Runset As… and save the runset you have created. This will save you from having to set this up again.
You should now be able to perform the extraction, so click Run PEX. If a pop up asks to overwrite the layout file, click OK to ensure Calibre sees any recent changes to your layout.
When Calibre has completed the extraction, a window will pop up showing the top level of the extracted netlist. Notice that there may be up to two additional netlists which will be included into the top level. The first will contain the RC networks and the second will contain the coupling capacitors. These netlists will also be found in the current working directory.

Simulating the post layout design

In the previous section, you created a layout based on your original schematic and extracted the parasitic parameters from the layout. In this section, you will learn how to:

Create a symbol for the post-layout netlist
Update the testbench
Include the extracted netlist in a simulation

Creating a new symbol

The easiest way to use your extracted netlist in a simulation is to create a new symbol for it, which can then be placed in your testbench.

Invoke Design Architect by typing the command adk_daic &. Click Open – Symbol in the Session Palette. Enter a name for your new symbol (something different than your original design) and Click OK. This will bring up a blank Symbol window.
In the Symbol_Draw palette, click Add – Rectangle, and then left-click and drag to create a rectangle. Note: The size of the rectangle is not really important at this point as you can always edit it later. To do this select the rectangle, right-click and chose Stretch:, and then left-click inside the rectangle to shrink it to that point and left-click outside the rectangle to stretch it to that point.
Now add the pins to your symbol by clicking Add – Pin in the symbol_draw palette. In the window that pops up choose the Pin Type: (either IN or OUT depending on the pin) then chose the Pin Placement: you want. Finally enter the name of the pin and click OK. If you have several pins that will have the same Pin Type/Placement, then enter all their names and create all of them at once. Repeat this process until all the pins on your design have been placed.
- Note: Generally, VDD and GND are considered to have a Pin Type: of IN.
- Note: When placing the pins on your symbol you should refer to the .subckt statement in the extracted netlist to ensure you have placed all the needed pins
Once you are happy with the look of you symbol it is time to add the needed properties. First, Unselect All either by pressing F2 or using the corresponding stroke. Then right-click and choose Properties (Logical)… from the Add menu. This will bring up the Add Multiple Properties window.
Enter the following two properties:
- Property Name ELEMENT
- Property Value X
- Property Name ASIM_MODEL
- Property Value <design>
Leave everything else as set and click OK.
Select a spot and left-click to place each property, and then click Text in the symbol_draw palette to bring up the symbol_text palette. Next click Edit – Text Attributes in the symbol_text palette. Now select the X which you just placed and this will bring up the Modify Property window. Set the Visibility Switch option to Hidden and click OK. This will make the ELEMENT property invisible when the symbol is placed in a schematic.
Check & Save the symbol. Once it passes all the checks you can close the symbol and proceed to the next section.

Updating the Testbench

Using the new symbol you can now update your testbench so that it uses the extracted netlist created by Calibre.

In the session palette chose Open – Schematic and Browse to find your original testbench. Click OK to open it.
Now select the symbol from you original design by left-clicking it and then press the delete key.
Next click Add – Instance in the schematic_edit palette. Browse and find the new symbol you just created and click OK, and then left-click in the schematic window to place the symbol. At this point you may need to redo some of the wiring in you testbench depending on how closely your new symbol matched the old one. Once all the wiring is correct proceed to the next section.

Simulate the new circuit

Now that the testbench has the new symbol in it we can set it up to use our extracted netlist and simulate our final design.

With your testbench open, click the Simulation button in the schematic_edit or adk_schematic_edit palette. This will put you in Design Context.
In the adk_schematic_sim palette choose Setup Other – Include to bring up the Set Include Paths window. Click Browse and find the top level netlist created by Calibre and click OK. Note: Do not include any of the other netlists created by Calibre as they are already included in the top level netlist.
Now create a new netlist by clicking Netlist – Write in the adk_schematic_sim palette. This will create a new netlist of your design using the new symbol.
Before proceeding with the simulation we must ensure that the pin lists in the two netlists are the same. Calibre list pins in the order it finds them in the layout where are Eldonet list pins based on their order on the symbol. As a result these two pin lists are often different. To correct this you will need to edit the extracted netlist to match the one generated by Eldonet. The netlist created by Eldonet will be located at <design>/<technology>a/<design>_<technology>.spi where design is the name of your design and technology is the ADK technology you are using. The Calibre netlist is generally of the form <design>.pex.netlist and should be located in your working directory. Open both with your favourite text editor or use the built in notepad by choosing MGC -> Notepad -> Open from the DA-IC menu bar.
You need to edit the .subckt line in the Calibre netlist to match the component instantiation in the Eldonet netlist. You should look for a line in the Calibre netlist similar to:
- .subckt <design> <pin list>
and change the order of its pin list to match the line in the Eldonet netlist which looks like:
- X1 <pin list> <design>
Once this is done you are ready to simulate your extracted netlist.

Note: If you are having trouble figuring out which net is which try labelling all the nets on your schematic that connect to your symbol and then re-netlist your testbench. This will get rid off the net names of the form N$###

Last Modified: 18 August, 2006 18:20:20.

Prepared by Simon Leung, leungks@itee.uq.edu.au

Modified by Balavelan Thanigaivelan, velan@itee.uq.edu.au