Hierarchical Design of a complex gate

Mentor Graphics Tutorial 7: Hierarchical Design of a complex gate with SDL procedure

Some material in the following tutorials are from David M. Zar (Washington University, St. Louis).

Manuals from Mentor Graphics Corporation has been used for additional reference

Introduction

In this tutorial, we assume:

You know the basics of SDL from the previous tutorials.
You have constructed the XOR gate as mentioned in Tutorial 02 and tested the functionality of it.

You will now use the SDL techniques to perform a hierarchical design of a 2-input exclusive-or gate (XOR), which can be built either from scratch or built from the NAND2 and INVERTER blocks you have designed earlier.

From the previous tutorials, you have made and tested the inverter and 2-input NAND cells. This tutorial walks you through the process of building a 2-input XOR gate using only these two cells. Of course, you could also build the XOR gate with just 2-input NAND gates, right?

The transistor width and length are defined in lambda units for layout, whereas length and width are in microns for simulation. So make sure you size the transistor in multiples of lambda, which is 0.09 for tsmc018 process. The minimum length one can choose is 2*lambda, which is 0.18um. Similarly the width of transistor must be chosen in multiples of lambda.

The procedure is to design the schematics with Design Architect and then test its functions. The layout mask for the gate is then drawn using SDL procedures. Here, you have 3 options:

Design using cell layouts from a library. This option is easiest, but is not very area efficient. Often, this option is referred as building a gate using standard gates (or standard cells). You can realise very complex circuitry based on the simple cells you've created. The simple cells (such as the NAND2 and Inverter) form a library of parts. In large companies, you may have access to many internal parts, or be able to purchase libraries which are optimised for performance or area or power. This is explored further in this tutorial.
Do a transistor layout using existing schematics. Since you've already drawn the schematics of the simpler components, why not just connect them up and use Mentor Graphics to generate the layout based on the schematic? It will save more area compared to the option above, but you still end up with too many transistors (WHY?).
Create a new schematics and a new layout. Start from scratch. Probably most area efficient, but take the longest time to make. This option is referred to as building a complex CMOS gate. What is the minimum number of transistors you need to build an XOR gate? (Answer: 12. WHY?)

Using customized hotkeys

In order to make it easier to perform layout, some of the features have been included in the custom hotkeys file.

Click here to download the hotkeys file and save it in your $MGC_WD folder. Some of the commands you have used in the previous tutorials have been scripted as functions into this customised hotkeys file. Alternatively, you can download the AMPLE file to your working directory. Then Click MGC drop down menu on IC Station, and choose Userware -> Load... Browse through your folder and choose the user_ic.ample file you just saved. You should be able to use the commands, but with little changes done to nwc and pwc functions.
Start IC Station adk_ic. Create a new cell or open an existing cell.
In order to enable the hotkeys, click Other -> hotkeys, while holding down the select button choose Load.
In the window that pops up with hotkeys settings, choose Custom option. Enter the location of the hotkeys file that you have downloaded by browsing or manually entering the full path.
Once the hotkeys have been loaded, the Hotkeys: On indicates the status on the right corner of the IC station window. In order to familiarise yourself with the hotkeys, click Other -> Hotkeys and while holding down the left mouse button choose Report.

Once you have familiarised yourself with the hotkeys, try to experiment it. Some of the frequently used hotkeys are mentioned here.

u	undo
w	view all
v	add via. Same as Function pp
g	add Poly to Metal1 contact. You should be able to move the Poly to Metal1 Contact to place it at the convenient location. This equivalent to command pc used before.
k	add N WELL contact. This key places same object as placed by the command nwc, but this time it asks for rows and columns to place the contacts. Often it is required to place multiple contacts, in order to ensure connectivity.
l	add P WELL contact. Again this key places same object as placed by the command pwc, but this time it asks for rows and columns to place the contacts. Often it is required to place multiple contacts, in order to ensure connectivity.
Shift-e (E)	Place Power Rails for a Standard Cell. Same as function pr.
e	Moving the Edge of a polygon, shape or path. Usage: Press 'e' key first. Then single click on the edge you want to move. Move the mouse to stretch the edge of the path or shape.
f	flip an object horizontally.
r	Rotate 90 deg.
p	Add Path
m	Move a shape

Layout of the XOR gate

Start IC Station adk_ic.
Create a new cell called my_xor2 and use the sdl viewpoint. Don't forget to set the other options on the menu as before! Under the Logic Loading Options the hierarchy should still be set to Flat.
Open the logic source to view the schematic: DLA Layout->Logic Open.
Now it is decision time. You can elect to use your hierarchical design to place existing cells that you (or someone else) created - option 1, or you can simply place transistors as you did in previous exercises - option 2. How will you proceed if you choose option 3?
This subsection lets you try to place transistors from scratch, without using any previous layout at all (refer to option 2 above).
1. You can select the components whose transistors you wish to place. In this example, we will assume that you wish to place all of the transistors that are included inside the inverters and NAND gates. Hence, you need to select all the transistors in your design. Simply make the schematic active by clicking on its window. The palette menu will change and one of the items is Sel. Use the Sel->Sel All Prim command to select all primitives (which are the transistors) in your design.
2. Once all transistors are selected, you can do an automatic placement with the AutoInst menu item. This will build some complex devices (merging diffusions and sharing gates where possible) and place them in your schematic.
3. Notice there are 16 transistors created. (hint: count the number of gates on the layout?) This is exactly how many you have in two inverters (2*2 = 4), and three NAND gates (3*4 = 12). Nothing fancy here, just placing transistors. Of course, you have no control over how the diffusion or well areas are shared, so routing this might be very difficult! Indeed, since we already have inverter and nand2 cells completed, we should simply use those to build our XOR cell.
4. Try to correspond the layout with the schematic. Locate where each of those transistors are on the layout. In this case, remember clicking the schematic will highlight the corresponding nets on the layout. Is the layout generated by Mentor Graphics correct? What needs to be done?
5. So delete the transistors you just placed in your layout. Select them all and hit the delete key. When prompted, select Delete All. All devices and nets should be gone. You would have a clean empty layout.
Taking a slightly easier option, you have decided to use hierarchical design techniques! The SDL procedure in IC station has been previously setup to search for default TSMC018 process to construct the schematics. Now since you have already made some cells based on those processes, you need to tell IC Station where to look for your cells. Do this with the Setup->SDL menu. Specify the search path to search for the cells that you created in your schematic design. The default was "$ADK/technology/ic/tsmc018_via". Those are the files necessary to create the customised cells. Remove the default directory and insert your directory. If your cells are already in the working directory, you could just enter ".".
Based on the components you created, IC Station will find the corresponding layout based on the symbol you have used in the Schematics. For example, if you created a component called "inv" and a cell called "inv", when trying to place this component, IC station will look for a cell called "inv", which it will find if it is in the search path, and use this cell for the "inv" symbol.
Once the path is set, IC can find your cells and you can continue with SDL placement of your logic. You can do a manual or auto placement in this mode. Firstly, click the schematic window to activate the DLA Layout options related to the schematic (remember, all menus on Mentor are context sensitive). If you perform an automatic placement with the AutoInst palette option, it will place your cells in a corresponding orientation to your schematic. Since you want to customise your cells, this option does not help you, much. You will still have to move your cells to the correct positions after placement. No good. Remove the cells.
Since you designed your cells and want to align them one next to each other, you should select the cells to place. In this case, you should select all five components in the schematic (or one at a time if you wish). Do the placement by clicking Inst in the palette menu (this is the schematic palette menu, activated by click on the schematic window first).
Usually it is a good practice to place more contacts in order to ensure connectivity. The command nwc was able to place only one contact for you. So in the previous tutorials you would have placed only one contact. Now, the nwc function has been modified to allow for row and column contact placements. In this layout, the gates have minimum of 3 or 4 contacts on the VDD and GND. You don't have to modify your individual gates as you will delete and place new contacts anyway.
Now place each cell. Look into the schematic window to see which cell you are placing. Of course, stick to the convention that the output on the right, input on the left, if possible. Use the maximise/minimise window functions and the zoom functions. If you have designed your cells in the same height with the same power/ground rail, they can be aligned as follows:

This is a peeked and flattened view. By default you will only see the ports and metal1 unless you did flatten the cells first and then "peek" (Context - Hierarchy - Peak) the cells.

There will be no need to route the power and ground rail. If those rail don't touch each other, there will be a yellow overflow line indicating that they have to be routed together. If the cell do not look like the figure, move them after placement until they form one row of cells. Exact placement order is not important, but try to keep the inverters close to the NAND gates they connected to.
Place the VDD and GND ports aligning with their corresponding port (power) rails on the cells. You could set up the port style as metal 2, but the power and ground ports don't make a connection to the existing metal 1 power rails. The schematic does not give you a simple option to choose VDD or GND ports anyway, so add a metal1 polygon extending over the entire length VDD or GND of the cell. Change those polygon to ports by selecting the polygon, Objects - Make - Port, with port type power and name VDD or GND. In this way, XOR gates can be aligned and used in the same way as your inverter and nand2 cells.
Before we put in the I/O ports, we should wire the gates together. Since you have designed your cells with ports on metal 2, you can use the automatic wiring tools to wire your cells together. Had you used poly for the ports, you would have to do manual wiring like you did within your cells.
1. Select the overflows that you wish to autoroute. To do this, set the selection filter to only select overflows via the Select - Setup Filter menu. In the dialog box, be sure only Overflow is selected.
2. If you select the area around the ports such that all of the overflows are included in the selected area, it will select all the overflows.
3. Use the AutoR palette item to perform the autoroute of the selected overflows. You will be prompted for probe extent. This is the area that defines the extent to which the autorouter will attempt to route the overflows. It will not place any routes outside the area you specify. You should draw a rectangle that encloses all of the overflows, leaving some space for the router to work on.
4. Check to make sure all overflows were routed. If any would not fit into the area, you need to make the extent larger or possibly move the ports to make room for all of the routes.
5. If the autorouter misses any overflows, you will have to manually route them yourself. Use your editing skills to make some room, then put in your routes (or use the autoroute function again).
6. The Comp palette item is for compacting the routing - it checks to see if there is any space which will reduce the overall footprint of the routes. You may decide to use it here to see if you can save some space.
Once the routing has been completed, you should change the n well and p well contacts. Select and delete the existing contacts. Be careful when selecting and deleting the layers.
Once you have deleted all the p well and n well contacts, you can place one single row of contacts by using the hotkeys k and l. Enter row to be 1 and desired number of columns to cover the whole gate. Alternatively, if you have enabled the Userware file you downloaded then use the commands pwc and nwc as you did before.
Now you should place the ports for the XOR gate. You need to setup the port style with the Setup->SDL->SDL Port Style palette option. You should also place them on metal 2, which is the default style. Select this in the dialog box.

Port

Y_exor2

out

Stretch, move and lengthen your routes so that the ports are connected and wired up. Be creative and think about the placements of these shapes.
Once you have completed the layout Select all and click on Edit -> Merge.
Your finished cell should look something like this:

Design Rule Checking, Verifications and Simulations with Extracted Parasitic parameters

Similar to previous exercises, we need to check whether the layout will comply with the design rules (DRC check). Then, we have to check whether the layout matches our schematics (LVS). Finally, we will simulate the design, with the parasitic parameters extracted from the layout, to get accurate timing information of our design.

Check for DRC errors as you have previously. If you have any DRC errors, you need to fix them before moving on.
Once DRC is done, you are ready to perform LVS. If the LVS check fails, you need to fix the problems before moving on to extraction.
Use Calibre for extraction as well.
You are now ready to simulate this cell with Parasitic.
A suggestion for testbench setup is as follows:

Setup the analysis for a transient analysis of duration 200 ns.
Pulse the input A_exor2 to 1.8 Volts at 100 ns.
Pulse the input B_exor2 to 1.8 Volts at time 50 ns and give it a period of 100 ns. This will cause all four input combinations to be tested in 200 ns.

Run the simulation and see the results.

You have now completed a hierarchical design using SDL procedures. Using the techniques discussed in this chapter and in the others, you should now be ready to design your own circuits of any complexity!

Last Modified: 31 August, 2006 18:02:21.

Prepared by Simon Leung, leungks@itee.uq.edu.au

Modified by Balavelan Thanigaivelan, velan@itee.uq.edu.au