Topic Choices

You need to choose from one of the following topics, in consultation with the course coordinator:

1. Thin versus wide – there is a growing trend in high-end designs towards wider internal structures in CPUs: wider buses, more instructions in parallel. This trend makes it difficult to scale up clock speed. Intel has stepped back from attempting to reach 4GHz in their mainstream designs. By contrast, the Cell design (a simplified PowerPC processor with 8 separate vector units) has been reported to run at speeds of up to 4GHz. AMD is achieving higher performance than some equivalent Intel designs at a lower clock speed. On the other hand, outside the CPU, there is a growing trend towards narrower buses, clocked at high speed, to achieve high throughput, rather than wider buses. Examples include FireWire and USB which have replaced parallel interfaces with more wires outside the box, Rambus, which introduced a narrower DRAM bus, and Hypertransport, a high-speed relatively narrow point-to-point interconnect. This project requires exploring one of two options:
   1. A narrow ALU, 16 bits wide internally, which can implement 32-bit arithmetic by multiple instructions. In this case, the project should explore the extent to which a narrower CPU could be faster than a wider CPU, by doing a logic design of selected instructions in both cases, and working out the time each instruction would take to execute, assuming like switching speeds in both design variations. This data should be used to estimate overall speed variation across the two alternatives.
   2. Bitstream processor. Some of the earliest microprocessors processed instructions only 1 bit at a time. The goal here is to determine whether a similar design could achieve competitive speed, as compared with a traditional word-parallel architecture. It may be possible in this case to do a less detailed comparison than with option 1(a), since the differences are bigger.
   Both of these options assume significant logic design skills.
2. Wake-up prediction logic. Dreamy memory is the idea of putting memory to sleep unless it is referenced. In earlier work, the speed loss from waiting for SDRAM to wake up from was significant. In this project, predictive prefetch would be added to the model, to attempt to reduce this speed loss. A predictor examining misses from the first-level (L1) cache would attempt to predict how far in future DRAM would next be needed. An existing simulator written in C++ could be adapted for this project. The project will include measurement of performance and energy use across a range of configurations, as well as an estimate of the complexity of the prediction logic.

   This project does not require significant logic design skills. Experience of C++ programming will be an advantage.

3. Design re-evaluation in the light of growth of embedded and mobile systems. The specific topic will be negotiated with the course coordinator. The idea is to evaluate previous trends in the development of CPUs, memories or other system components, and choose an area where design trade-offs may have to be re-evaluated given the increasing focus on small-scale devices where energy is a first class concern.

   This project can take many different directions, so choosing this option requires that significant time be spent at the start in defining the topic.

4. Multiscale computing. This project requires evaluation of design principles which work at very small and very large scales. For example, an instruction set design which supports both very large and very small address spaces efficiently would fit this criterion. This project requires an analysis of design features of processsors aimed at both very large and very small systems, and producing design criteria for new processors which would work well at all points of the design space with minimal compromises.

Marking

The project counts for 60% of course marks, broken down as follows, with mark sheets:

• proposal talk week 6: 10% (mark sheet PDF)
• draft report week 9: if not submitted, no credit for peer reviews (this will not be marked but you will receive reviews from the lecturer plus 3 other class members)
• peer reviews of other class members’ draft report due week 10: 5% credit provided you submitted a draft paper (form for review, plain text; mark scheme for reviews PDF)
• final presentation week 11: 10% (mark sheet PDF – the same as for the first talk, but this time, results will be evaluated, rather than your project plan)
• final project report (written in the style of a technical paper) week 12: 35% (mark sheet PDF)