CSSE7013 2005
Additional Reading

Papers with copyright restrictions are accessible through the university library; in other cases, local copies are available to reduce net traffic.

Hardware/Software Codesign

AA Jerraya and W Wolf. Hardware/Software Interface Codesign for Embedded Systems, Computer, vol. 38 no. 2 February 2005, pp 63-69
available through IEEE Xplore [PDF 148KB]
P Machanick, P Salverda and L Pompe. Hardware-Software Trade-Offs in a Direct Rambus Implementation of the RAMpage Memory Hierarchy, Proc. ASPLOS-VIII Eighth International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, October 1998, pp. 105-114 (local copy) [PDF 129KB]

Available free off the net:

Various papers are obtainable via IBM's Cell publications web site:

Pham, D., Asano, S., Bolliger, M., Day, M. N., Hofstee, H. P., Johns, C., Kahle, J., Kameyama,A., Keaty, J.,Masubuchi, Y., Riley,M., Shippy, D., Stasiak, D., Suzuoki, M., Wang, M., Warnock, J., Weitzel, S., Wendel, D., Yamazaki, T., and Yazawa, K. (2005). The design and implementation of a first-generation CELL processor. In ISSCC 2005 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pages 184–185,592, San Francisco.
Dhong, S. H., Takahashi, O.,White, M., Asano, T., Nakazato, T., Silberman, J., Kawasumi,
A., and Yoshihara, H. (2005). A 4.8GHz fully pipelined embedded SRAM in the streaming processor of a CELL processor. In ISSCC 2005 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pages 486–487,612, San Francisco.
Krewell, K. (2005). Cell moves into the limelight. Microprocessor Report, 14 February.

Various papers from web sites and digital libraries:

Hiromitsu Kimura, Kostas Pagiamtzis, Ali Sheikholeslami and Takahiro Hanyu. A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices, Proc. 34th Int. Symp. on Multiple-Valued Logic (ISMVL’04), Toronto, Canada, May 2004, pp 340-345.

last edited Monday, 25 July 2005 at 2:34 PM.