Xilinx ISE, Spartan and IO Board Tutorial

Some information, figures and diagrams (as marked) in this tutorial are used with permission from Digilent Inc. and are copyrighted by Digilent Inc.

This tutorial describes how to implement a VHDL design using Xilinx ISE and the Spartan 2E FPGA and IO Boards. This tutorial follows the previous tutorial. This tutorial is comprised of six sections:

Xilinx ISE design implementation
Digilent Spartan FPGA Board (D2FT)
Digilent IO 5 Board (DIO5)
DIO5 Signal Description
Example Design - Race Timer
References and Links

Please report any problems to your tutors via email.

Xilinx ISE Implementation and Programming

This section describes how to assign FPGA pins to the various signals of your design. As well, the steps used to generate a programming file are also described. This tutorial follows the previous tutorial.

Implementation Constraints

In order to assign pins to the signals in your top level entity, you need to create a implementation constraints file. You can do this by using the ‘Project/New sources’ menu. Make sure that you associate the implementation constraints file with your top level entity. Once the file (.ucf) has been created, double click on it to open the constraints editor. Click on the ports tab. Enter the pin assignments (See DIO5 Signal Description) in the location fields of your signals. Also prohibit the configuration pins by using the ‘Prohibit Pin Locations’ button. When you have finished, save and exit. Click on your top level VHDL module in the module view window to continue.

Figure 1: Xilinx Constraints Editor Window

Implementation

Once your design has synthesized without warnings, you can implement the design by double clicking on the implement option in the process view window. You can expand this option to view the reports. The pad report will contain your pin assignments which should be the same as described in the (.ucf) file.

Programming

A programming file is created by double clicking on the ‘Generate programming file’ option in the process window. Once the file has been generated, you can program the device using the configure option. Before you click on the configure option, ensure that the D2FT board is turned on (red LED will be lit). Double click on the configure option to open the IMPACT window. Select the following options in the front menu by pressing next.

Configure devices

Boundary-Scan Mode

Automatically connect to cable and identify Boundary-Scan Chain

If the device has been successfully recognized, an icon will appear in the window. If errors occur, please check that the parallel cable is connected and ensure that the red power on LED on the board is on. A file select window will open, please select your configuration (.bit) file. Ignore any warnings that occur (Warning 1049). Right click on the icon and select program. Do not select any options on the menu, only press OK. Once programming is complete, a blue "programming succeeded" label will appear. Please note that the Impact program can be accessed under the "Xilinx ISE 6\Accessories" folder on the Windows Start Bar.

Figure 2: "Programming succeeded" Impact window.

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Digilab Spartan FPGA Board (D2FT)

The Digilent Spartan D2FT board has a SpartanII 2S400E FPGA, onboard pushbutton, LED, 50MHz clock generator and a JTAG programmer port. The JTAG programmer port is the parallel IO module. There are 6 connection headers (A1, A2, B1, B2, C1 & C2F) that can be used to make connections to the FPGA. The table 2 shows the FPGA pins connected to the LED, 50MHz clock generator and pushbutton. The pushbutton can be used as a general purpose input. Pin assignments for the D2FT board are alphanumeric. Please see the DIO5 Signal Description for more information regarding the IO Board pin assignments. Table 1 shows the project property settings that your project must conform to in order to use the D2FT Board. An example project using the D2FT board is given the example design section.

Table 1: Project Property Settings

Device Family	Spartan 2E
Device	XC2S400E
Package	ft256
Speed Grade	-6

Table 2: Onboard peripheral pin assignments

Peripheral	Spartan D2FT pin assignment
LED	C15
Pushbutton (BTN1)	A12
50MHz clock generator	B8

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Digilent IO Board 5 (DIO5)

The Digilab Digital I/O board 5 (DIO5) is one of several expansion boards designed to connect with Digilab system boards. The DIO5 board provides an assortment of frequently used digital I/O devices, many of which are controlled by an on-board Xilinx XC3256 CPLD. The CPLD provides a bus interface to simplify communications with Digilab system boards. Please see the Digilent DIO5 Schematic and Digilent DIO5 user manual for more information.

DIO5 board features include:

A XC3256 CPLD for I/O device and system bus control;
A 16x2 character LCD with integral Samsung controller IC;
A four digit seven-segment LED display;
16 individual LEDs of various colors;
An 8-bit VGA port;
A 16-button keypad;
8 slide switches;
A PS2 mouse/keyboard port;
An on board 5VDC regulator.

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Function Description of Switches, LEDs, Pushbuttons and Seven Segment Display

The seven segment display, LEDs, switches and pushbuttons are accessed by writing and reading various registers on the XCR3256 CPLD. The switches and six of the pushbuttons can be accessed without reading the CPLD. See DIO5 Signal Description. Each bit in the registers used to access the switches, pushbuttons or LEDs corresponds to a particular switch, pushbutton or LED on the DIO5 board. The CPLD implements a seven segment display controller. The seven segment controller will take a normal 4 bit number and display the corresponding hexadecimal value. Two registers are used to access the seven segment displays. Each seven segment 8 bit register corresponds to two (upper, lower) seven segment digits. The upper 4 bits of each seven segment register correspond to the digit that will be displayed on the upper seven segment digit. The lower 4 bits of each seven segment register corresponds to the digit that will be displayed on the lower seven segment digit. The timing diagrams for reading and writing various registers on the CPLD are shown below. A clock signal must be assigned to SCLK and LCLK in order for the CPLD register reads and writes to operate. The table below gives the addresses of the registers that can be accessed.

Table 3: CPLD Address Space

Register	Address
LEDs (7 to 0)	0
LEDs (15 to 8)	1
Seven Segment Display (Lower 2 digits)	2
Seven Segment Display (Upper 2 digits)	3
LCD registers	4

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Function Description of PS2 Interface and Keyboard Protocol

The AT keyboard uses open collector drivers so that either the keyboard or an attached host device can drive the two-wire bus (if the host device will not send data to the keyboard, then the host can use simple input-only ports). On the DIO5 board, the clock and data signals (KCLK and KDAT) bypass the CPLD, and are connected directly to pins on the J2/P2 connector. A PS2-style keyboard uses scan codes to communicate key press data (nearly all keyboards in use today are PS2 style). Each key has a single, unique scan code that is sent whenever the corresponding key is pressed. If the key is pressed and held, the scan code will be sent repeatedly once every 100ms or so. When a key is released, a "F0" key-up code is sent, followed by the scan code of the released key. If a key has a "shift" character that is different than the non-shift character, the same scan code is sent whether the shift key is pressed or not, and the host device must determine which character to use. Some keys, called extended keys, send an "E0" ahead of the scan code (and they may send more than one scan code). When an extended key is released, a "E0 F0" key-up code is sent, followed by the scan code. Scan codes and ASCII characters for alphabetical keys are shown in the Table below.

Table 4: Character\Scan code\ASCII character

Character	Scan Code (hex)	ASCII Character (hex)
A	1C	41
B	32	42
C	21	43
D	23	44
E	24	45
F	2B	46
G	34	47
H	33	48
I	43	49
J	3B	4A
K	42	4B
L	4B	4C
M	3A	4D
N	31	4E
O	44	4F
P	4D	50
Q	15	51
R	2D	52
S	1B	53
T	2C	54
U	3C	55
V	2A	56
W	1D	57
X	22	58
Y	35	59
Z	1A	5A

The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by 8-bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. The keyboard generates 11 clock transitions (at around 20 - 30KHz) when the data is sent, and data is valid on the falling edge of the clock. This is shown in the figure below.

Figure 3: PS2 Interface

Table 5: PS2 Interface Connections

PS2 Inputs	DIO5 Signal	D2FT Board Connection
Keyboard Clock	KCLK	D22
Keyboard Data	KDAT	D21

If you want to know more about the AT keyboard, extra scan codes or ASCII values, please see the reference and links section.

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Function Description of LCD

The LCD display is a 16 character, 2 line display from the Okaya company (Okaya part number RC1602D). The display uses a KS0066 Samsung controller that has a character-generator ROM (CGROM) containing 208 preset 5x8 character patterns, a character-generator RAM (CGRAM) that can hold 8 user-defined 5x8 characters, and a display data RAM (DDRAM) that can hold 80 character codes. Character codes written into the DDRAM serve as indexes into the CGROM (or CGRAM). Writing a character code into a particular DDRAM location will cause the associated 5x8 character pattern to appear at the corresponding display location. The display positions can be shifted left or right by setting a bit in the instruction register (IR). The write-only IR is used to direct display operations (such as clear display, shift left or right, set DDRAM address, etc). Available instructions are shown in the rightmost column of the table below, together with the IR codes. A busy flag is available to indicate whether the display has competed the last requested operation; prior to initiating a new operation, the flag can be checked to see whether the previous operation has been completed.

The display has more DDRAM locations than can be displayed at any given time. DDRAM locations 00H to 27H map to the first display row, and locations 40H to 67H map to the second row. Normally, DDRAM location 00H maps to the upper left display corner, and 40H to the lower left. Shifting the display left or right can change this mapping. The display uses a temporary data register (DR) to hold data during DDRAM /CGRAM read or write operations, and an internal address register to select the RAM location. Address register contents, which can be set via the IR, are automatically incremented after each read or write operation. The LCD display uses ASCII character codes. Codes up through 7F are standard ASCII (which includes all "normal" alphanumeric characters). Codes above 7F produce various international characters – please see the manufacturers data sheet for more information on international codes. The Seikio LCD datasheet contains a more detailed description on how to use the LCD.

Figure 8: LCD Display Position Maps ©Digilent.

Figure 4: LCD Instruction Set ©Digilent.

LCD Signals

The LCD display is connected to the DIO5 board by a 16-pin connector. The eight data bus signals (DB7-DB0) and three strobes (RS,R/W, LCDEN) are connected directly to the B connector on the DIO5 board (note the data lines are common with the DIO5 data bus), so the LCD can be controlled from the D2FT board. Bus timings are shown below. Note that the enable signal (LCDEN) serves as both output enable and write strobe (with an active falling edge) depending on the state of the Read/Write (R/W) signal. Also note that some of the strobe signals are shared with the DIO5 strobe signals. When reading or writing to the LCD, the other DIO5 signals such as CS, OE, SCLK and ADR5-ADR1 need to be driven as well. Address lines ADR5, ADR4, ADR2, ADR1 need to be driven low and ADR3 needs to be driven high. Address line ADR0 is driven by RS. See the LCD read\write timing diagrams for more details.

Table 6: Shared LCD and DIO5 signals

LCD Signal Name	Shared DIO5 signals
DB7-DB0	DB7-DB0
LCDEN	-
R/W	WE
RS	ADR(0)

Figure 5: LCD Read\Write Timing Diagram ©Digilent.

LCD Startup Sequence

The manufacturer requires that a startup sequence with specific timings be followed to ensure proper LCD operation. After power-on, at least 20ms must elapse before the function-set instruction code can be written to set the bus width, number of lines, and character patterns (8-bit interface, 2 lines, and 5x8 dots are appropriate). After the function-set instruction, at least 37us must elapse before the display-control instruction can be written (to turn the display on, turn the cursor on or off, and set the cursor to blink or no blink). Then after another 37us, the display-clear instruction can be issued, followed by a 1.52ms delay. The entry-mode instruction code is then issued which is used to set the address increment (or address decrement) mode, and display shift mode (on or off). After the entry-mode instruction is issued, the Set CGRAM and Set DDRAM address instructions are then issued. Once this sequence is complete, ASCII data can be written into the DDRAM to cause information to appear on the display.

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DIO5 Signal Description

D0 - D7 : Data input/output bus of the CPLD. The data to be read or written to the register will be placed on these pins.
AR0: AR5 : Address input of the CPLD. The addresses of the registers to be accessed must be placed on these pins.
SW1 : SW8 : Outputs of slide switches. The outputs of the slide switches can also be accessed through the CPLD.
CS, OE, WE : Control signals used for CPLD bus read and write operations
SCLK & LCLK : Clock signal input of the CPLD. This pin must be assigned a clock signal in order for the CPLD to function.
BOUTA : BOUTF : Outputs of pushbuttons A to F. In order to use these pushbutton outputs, SCLK and LCLK must have a clock signal. These pushbuttons are passed through a 'debouncing' filter in the CPLD.
BCOD0 : BCOD3l : Four bit binary output of the pushbutton line counter. When any of pushbuttons 0 to 9 are pressed, its corresponding binary number will be placed on these pins, i.e. pressing pushbutton 9, BCOD3: BCOD1 = 1001 (binary).
KDAT, KCLK : Keyboard data and clock outputs.
LCDEN : Enable signal of LCD.
HS, VS, RED, GRN, BLU : Signals used for the VGA interface.
IO -01 : IO - 06, CLK2 : Extra Input\Output signals of the CPLD.

Please see the Digilent DIO5 Interconnection Sheet, Digilent DIO5 Schematic, Digilent DIO5 user manual and Digilent D2FT schematic for more information.

Example Design - Race Timer

The project for the 2 digit race timer is provided:

Spartan D2FT Board Race timer

You can open up the timer.bit file in the Impact program to program the board. The race timer assumes that the DIO5 board is connected to port A of the D2FT board. Reset is SW1 and is active high, pushbutton is the BTN1: black pushbutton on the D2FT Board. You will need to press the pushbutton once to start the timer. Then press the pushbutton to stop the timers. Pushbutton bounce does occur, so be careful when pressing the pushbutton. Don't hold the pushbutton down for a long period of time.

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