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High Performance Computing
Introduction
An embedded application requires a flexible software and hardware platform to run on, especially when the demands placed by end-user is ever increasing. FPGAs (Field Programmable Gate Array) and RSoC (Reconfigurable System-on-Chip) hardware platforms enable implementation of a solution that is easily upgradable both in terms of hardware and software.
Distributed multi-processor hardware enable a problem to be solved much faster, than single processor systems, and can be implemented on FPGAs. FPGA elements such as PowerPC, MicroBlaze, hardware IP (Intellectual Property) blocks that enable a distributed system, need a dedicated hardware and software communication architecture to provide the required application performance.
Motivation
The motivation for this research stems from "A one-size-fits-all ideology is not the best approach to the various challenges in the embedded systems space". Instead, application-specific, heterogeneous software and hardware architectures emerge as a potential solution to the challenges of high density, high performance, and low power consumption in the reconfigurable computing arena.
Multiprocessor System-on-Chip (MPSoC) systems are a lot more favourable than uni processor systems to satisfy the stringent performance requirements of many embedded systems applications, because of an increase in computation and communication capacity. Hybrid
MultiProcessor Cluster-on-Chip (HMPCoC) systems provide hardware and software reconfigurability, general-purpose CPUs, dedicated IP cores, I/O interfaces and a flexible communication fabric to improve data-intensive, time-sensitive application performance.
Goal
To efficiently utilise the flexibility and performance provided by reconfigurable hardware platform, an equally flexible and dynamic software platform is necessary. Previously, parallel programming constructs such as Message Passing Interface (MPI), have successfully supported parallel processing on large homogeneous systems. MPI, is a specification for implementing a Message Passing (MP) paradigm that defines standard communication mechanisms to enable parallel processing with multiple Processing Elements (PEs). MPI is standardised and extensively used in the High Performance Computing (HPC) arena.
To leverage the performance and flexibility of Hybrid MultiProcessor Cluster-on-Chip (HMPCoC) systems in a heterogeneous environment, a standardised parallel communication architecture based on message passing (MP) is critical. The goal is to provide a unified hardware and software Message Passing Interface (MPI) module for Message Passing (MP) communication architecture that will enable Hybrid MultiProcessor Cluster-on-Chip (HMPCoC) to be flexible and scalable platform that satisfies performance constraints and be utilised as a coherent computational resource.
Papers
Syed, I., Williams, J., and Bergmann, N. 2006. A Reconfigurable Cluster-on-Chip Architecture with MPI Communication Layer. Field Programmable Logic (FPL) 2007, The Netherlands.
Williams, J., Syed, I., and Bergmann, N. 2006. A Reconfigurable Cluster-on-Chip Architecture with MPI Communication Layer. Field Custom Computing Machines (FCCM) 2006, USA.
Wu, J., Syed, I., Williams, J. Creating a simple uCLinux ready Microblaze Design. Technical report 2006.
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