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Re: [microblaze-uclinux] Questions about the Ethernet interface
Hi Peter,
Peter Ryser wrote:
> in the attachment a complete MHS file as we use it on the Insight board
> (2VP4-FF672) plus the UCF. This design works on PPC.
>
> Ignore the first warning - it's a problem with the PHY detection
> routine. You should not see the problems further down, i.e. the error 19
> stuff and the transmit buffer thing.
OK a bit more progress, it seems in my editing of xparameters.h I had
disabled MII support, so the driver didn't think it could do it. Fixed
that, now I don't get any warnings on startup, but still problems on the
intyerface.
Basically the problem is that the PHY link is never coming up. The
driver queries the PHY (via MII) to get duplex and link status, then
compares PHY link status with interface link status. The interface
thinks it's up, but the PHY says it is down, so the driver shutsdown,
reporting a lost carrier.
There's a curious comment in the driver, for the poll_mii() function:
/*
* This routine is used for two purposes. The first is to keep the
* EMAC's duplex setting in sync with the PHY's. The second is to keep
* the system apprised of the state of the link. Note that this driver
* does not configure the PHY. Either the PHY should be configured for
* auto-negotiation or it should be handled by something like mii-tool.
*/
static void
poll_mii(unsigned long data)
...
So, do I need to explictly tell the PHY to bring up the link? If so,
how do I do that?
Thanks,
John
>
> - Peter
> before
> John Williams wrote:
>
>> Hi Peter,
>>
>> Peter Ryser wrote:
>>
>>> I'd like to encourage you to fix the xparameters.h to match up the
>>> defines used in the drivers instead of changing the drivers. As a
>>> result you will get EDK integration for free.
>>
>>
>>
>> Using the xilinc_emac driver, when it initialises the module, and
>> calls the probe() function, I receive the warning
>>
>> eth0: No PHY detected. Assuming a PHY at address 0.
>>
>> After boot up, I configure the interface (ifconfig), and that seems to
>> partially work (sets the MAC and IP addresses properly), however I
>> then get more PHY-related errors:
>>
>> eth0: Could not read PHY control register; error 19
>> eth0: Could not read PHY control register; error 19
>> eth0: Terminating link monitoring
>>
>> If I try to send any packets through this interface (with ping, which
>> works fine with the loopback interface "lo", hooray!), it crashes
>> after multiple errors of
>>
>> eth0: Could not transmit buffer
>> eth0: Could not transmit buffer
>> ...
>>
>>
>> I've lifted the MHS and UCF configuration from an existing Insight
>> ethernet demo (using the xil_net stuff), so that should all be fine?
>>
>> I've dug into the driver code, basically it seems to relate to the MII
>> PHY interface.
>>
>> PORT ETH_MDC = ETH_MDC, DIR = IN
>> PORT ETH_MDIO = ETH_MDIO, DIR = IN
>>
>> Just looking at it, shouldn't the ETH_MDIO (which is the phy_mii_data)
>> be INOUT? I know nothing about the MII interface, but I assume at
>> least that it's two way?
>>
>> Anyway, continuing on...
>>
>> BEGIN opb_ethernet
>> PARAMETER INSTANCE = ether
>> PARAMETER C_FAMILY = virtex2
>> PARAMETER HW_VER = 1.00.k
>> PARAMETER C_DMA_PRESENT = 1
>> PARAMETER C_DMA_INTR_COALESCE = 1
>> PARAMETER C_OPB_CLK_PERIOD_PS = 15000
>> PARAMETER C_BASEADDR = 0xC0000000
>> PARAMETER C_HIGHADDR = 0xC0003FFF
>> PORT OPB_Clk = sys_clk
>> PORT OPB_Rst = sys_rst
>> PORT PHY_col = ETH_COL
>> PORT PHY_crs = ETH_CRS
>> PORT PHY_Mii_clk = ETH_MDC
>> PORT PHY_Mii_data = ETH_MDIO
>> PORT PHY_rx_clk = ETH_RXC
>> PORT PHY_rx_data = ETH_RXD
>> PORT PHY_dv = ETH_RXDV
>> PORT PHY_rx_er = ETH_RXER
>> PORT PHY_tx_clk = ETH_TXC
>> PORT PHY_tx_data = ETH_TXD
>> PORT PHY_tx_en = ETH_TXEN
>> PORT PHY_tx_er = ETH_TXER
>> PORT PHY_rst_n = PHY_RESETn
>> PORT Freeze = net_gnd
>> PORT IP2INTC_Irpt = ethernet_interrupt
>> BUS_INTERFACE MSOPB = d_opb_v20
>> END
>>
>>
>>
>> # Timespecs and output constraints for ethernet
>> NET "eth_rxc" TNM_NET = "RXCLK_GRP";
>> NET "eth_txc" TNM_NET = "TXCLK_GRP";
>> TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;
>> TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;
>> NET "eth_rxc" USELOWSKEWLINES;
>> NET "eth_txc" USELOWSKEWLINES;
>> NET "eth_txc" MAXSKEW= 2.0 ns;
>> NET "eth_rxc" MAXSKEW= 2.0 ns;
>> NET "eth_rxc" PERIOD = 40 ns HIGH 14 ns;
>> NET "eth_txc" PERIOD = 40 ns HIGH 14 ns;
>> NET "eth_rxd<3>" NODELAY;
>> NET "eth_rxd<2>" NODELAY;
>> NET "eth_rxd<1>" NODELAY;
>> NET "eth_rxd<0>" NODELAY;
>> NET "eth_rxdv" NODELAY;
>> NET "eth_rxer" NODELAY;
>> # NET "eth_crs_dv" NODELAY;
>> NET "eth_col" NODELAY;
>> NET "eth_txc" TNM_NET = "eth_txc";
>> NET "eth_rxc" TNM_NET = "eth_rxc";
>>
>> What sort of MHS setup are you using for PPC/linux/ethernet projects?
>> I assume you've had it going with the P160 comms module on an insight
>> board?
>>
>> thanks,
>>
>> John
>>
>>
>> ___________________________
>> microblaze-uclinux mailing list
>> microblaze-uclinux@itee.uq.edu.au
>> Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
>> Mailing List Archive :
>> http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
>>
>
> ------------------------------------------------------------------------
>
>
>
> # Parameters
> PARAMETER VERSION = 2.1.0
>
>
> PORT sys_clk_raw = sys_clk_raw, DIR = IN
> PORT system_reset = system_reset, DIR = IN
> PORT cpu_halt = cpu_halt, DIR = IN
> PORT cpu_tck = cpu_tck, DIR = IN
> PORT cpu_tdi = cpu_tdi, DIR = IN
> PORT cpu_tdo = cpu_tdo, DIR = OUT
> PORT cpu_tms = cpu_tms, DIR = IN
> PORT cpu_trst = cpu_trst, DIR = IN
> PORT sdram_clk = sdram_clk, DIR = OUT
> PORT sdram_clk_en = sdram_clk_en, DIR = OUT
> PORT sdram_cs_n = sdram_cs_n, DIR = OUT
> PORT sdram_ras_n = sdram_ras_n, DIR = OUT
> PORT sdram_cas_n = sdram_cas_n, DIR = OUT
> PORT sdram_we_n = sdram_we_n, DIR = OUT
> PORT sdram_data_mask = sdram_data_mask, VEC = [0:3], DIR = OUT
> PORT sdram_ba = sdram_ba, VEC = [0:1], DIR = OUT
> PORT sdram_abus = sdram_abus, VEC = [0:11], DIR = OUT
> PORT sdram_dbus = sdram_dbus, VEC = [0:31], DIR = INOUT
> PORT sram_addr = sram_addr, VEC = [0:31], DIR = OUT
> PORT sram_data = sram_data, VEC = [0:31], DIR = INOUT
> PORT sram_cen = sram_cen, VEC = [0:0], DIR = OUT
> PORT sram_oen = sram_oen, DIR = OUT
> PORT sram_wen = sram_wen, DIR = OUT
> PORT sram_ben = sram_ben, VEC = [0:3], DIR = OUT
> PORT sram_rst = sram_rst, DIR = OUT
> PORT gpio = gpio, VEC = [0:3], DIR = INOUT
> PORT ETH_TXC = ETH_TXC, DIR = IN
> PORT ETH_RXC = ETH_RXC, DIR = IN
> PORT ETH_CRS = ETH_CRS, DIR = IN
> PORT ETH_RXDV = ETH_RXDV, DIR = IN
> PORT ETH_RXD = ETH_RXD, VEC = [3:0], DIR = IN
> PORT ETH_COL = ETH_COL, DIR = IN
> PORT ETH_RXER = ETH_RXER, DIR = IN
> PORT ETH_TXEN = ETH_TXEN, DIR = OUT
> PORT ETH_TXER = ETH_TXER, DIR = OUT
> PORT ETH_TXD = ETH_TXD, VEC = [3:0], DIR = OUT
> PORT ETH_MDC = ETH_MDC, DIR = INOUT
> PORT PHY_RESETn = PHY_RESETn, DIR = OUT
> PORT ETH_MDIO = ETH_MDIO, DIR = INOUT
> PORT Uart1_ctsN = Uart1_ctsN, DIR = IN
> PORT Uart1_rtsN = Uart1_rtsN, DIR = OUT
> PORT Uart1_sin = Uart1_sin, DIR = IN
> PORT Uart1_sout = Uart1_sout, DIR = OUT
> PORT TRSTNEG = TRSTNEG, DIR = IN
> PORT HALTNEG = HALTNEG, DIR = IN
> PORT sram_cefn = net_vcc, DIR = OUT
> PORT sysace_clk = sysace_clk, DIR = IN
> PORT sysace_clk_oe_n = net_gnd, DIR = OUT
> PORT sysace_mpce = sysace_mpce, DIR = OUT
> PORT sysace_mpa = sysace_mpa, DIR = OUT, VEC = [6:0]
> PORT sysace_mpd = sysace_mpd, DIR = INOUT, VEC = [7:0]
> PORT sysace_mpirq = sysace_mpirq, DIR = IN
> PORT sysace_mpoe = sysace_mpoe, DIR = OUT
> PORT sysace_mpwe = sysace_mpwe, DIR = OUT
>
>
> # Sub Components
> BEGIN dcm_ip
> PARAMETER INSTANCE = dcm_logic
> PORT sys_clk = sys_clk_raw
> PORT bus_clk = sys_clk
> PORT cpu_clk = cpu_clk
> PORT dcm_lock = dcm_lock
> END
>
> BEGIN proc_sys_reset
> PARAMETER INSTANCE = reset_block
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_EXT_RST_WIDTH = 4
> PARAMETER C_EXT_RESET_HIGH = 0
> PARAMETER C_AUX_RST_WIDTH = 1
> PARAMETER C_NUM_BUS_RST = 1
> PORT Slowest_sync_clk = sys_clk
> PORT Ext_Reset_In = system_reset
> PORT System_Reset_Req = C405RSTSYSRESETREQ
> PORT Rstc405resetsys = RSTC405RESETSYS
> PORT Bus_Struct_Reset = sys_bus_reset
> PORT Dcm_locked = dcm_lock
> END
>
> BEGIN my_jtag_logic
> PARAMETER INSTANCE = my_jtag_logic_0
> PARAMETER HW_VER = 1.00.a
> PORT C405JTGTDO = c405jtagtdo
> PORT C405JTGTDOEN = c405jtagtdoen
> PORT CLK = sys_clk
> PORT CPU_HALT = cpu_halt
> PORT CPU_TCK = cpu_tck
> PORT CPU_TDI = cpu_tdi
> PORT CPU_TDO = cpu_tdo
> PORT CPU_TMS = cpu_tms
> PORT CPU_TRST = cpu_trst
> PORT ACE_RELEASE_HALT = net_vcc
> PORT DBGC405DEBUGHALT = dbgc405debughalt
> PORT JTGC405TCK = jtgc405tck
> PORT JTGC405TDI = jtagc405tdi
> PORT JTGC405TMS = jtagc405tms
> PORT JTGC405TRSTNEG = jtagc405trstneg
> PORT RST = C405RSTSYSRESETREQ
> END
>
> BEGIN ppc405
> PARAMETER INSTANCE = PPC405_i
> PARAMETER HW_VER = 1.00.a
> BUS_INTERFACE DPLB = plb_bus
> BUS_INTERFACE IPLB = plb_bus
> PORT CPMC405CLOCK = cpu_clk
> PORT PLBCLK = sys_clk
> PORT CPMC405CORECLKINACTIVE = net_gnd
> PORT CPMC405CPUCLKEN = net_vcc
> PORT CPMC405JTAGCLKEN = net_vcc
> PORT CPMC405TIMERTICK = net_vcc
> PORT CPMC405TIMERCLKEN = net_vcc
> PORT MCPPCRST = net_vcc
> PORT TIEC405DISOPERANDFWD = net_vcc
> PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
> PORT RSTC405RESETCHIP = RSTC405RESETSYS
> PORT RSTC405RESETCORE = RSTC405RESETSYS
> PORT RSTC405RESETSYS = RSTC405RESETSYS
> PORT EICC405EXTINPUTIRQ = interrupt
> PORT EICC405CRITINPUTIRQ = net_gnd
> PORT JTGC405TCK = jtgc405tck
> PORT JTGC405TDI = jtagc405tdi
> PORT JTGC405TMS = jtagc405tms
> PORT JTGC405TRSTNEG = jtagc405trstneg
> PORT C405JTGTDO = c405jtagtdo
> PORT C405JTGTDOEN = c405jtagtdoen
> PORT DBGC405DEBUGHALT = dbgc405debughalt
> END
>
> BEGIN plb_bram_if_cntlr
> PARAMETER INSTANCE = plbbram_cntlr
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_BASEADDR = 0xFFFF8000
> PARAMETER C_HIGHADDR = 0xFFFFFFFF
> BUS_INTERFACE PORTA = porta
> BUS_INTERFACE SPLB = plb_bus
> END
>
> BEGIN bram_block
> PARAMETER INSTANCE = bram1
> PARAMETER HW_VER = 1.00.a
> BUS_INTERFACE PORTA = porta
> END
>
> BEGIN plb_sdram
> PARAMETER INSTANCE = plb_sdram_memory
> PARAMETER HW_VER = 1.00.c
> PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1
> PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 1
> PARAMETER C_SDRAM_TMRD = 2
> PARAMETER C_SDRAM_TWR = 20000
> PARAMETER C_SDRAM_TCCD = 1
> PARAMETER C_SDRAM_TRAS = 48000
> PARAMETER C_SDRAM_TRC = 70000
> PARAMETER C_SDRAM_TRFC = 70000
> PARAMETER C_SDRAM_TRCD = 19000
> PARAMETER C_SDRAM_TRRD = 16000
> PARAMETER C_SDRAM_TRP = 19000
> PARAMETER C_SDRAM_TREF = 64
> PARAMETER C_SDRAM_REFRESH_NUMROWS = 4096
> PARAMETER C_SDRAM_CAS_LAT = 2
> PARAMETER C_SDRAM_DWIDTH = 32
> PARAMETER C_SDRAM_AWIDTH = 12
> PARAMETER C_SDRAM_COL_AWIDTH = 9
> PARAMETER C_SDRAM_BANK_AWIDTH = 2
> PARAMETER C_PLB_CLK_PERIOD_PS = 10000
> PARAMETER C_SDRAM_TREFI = 15625000
> PARAMETER C_BASEADDR = 0x00000000
> PARAMETER C_HIGHADDR = 0x01FFFFFF
> BUS_INTERFACE SPLB = plb_bus
> PORT SDRAM_Clk = sdram_clk
> PORT SDRAM_CKE = sdram_clk_en
> PORT SDRAM_CSn = sdram_cs_n
> PORT SDRAM_RASn = sdram_ras_n
> PORT SDRAM_CASn = sdram_cas_n
> PORT SDRAM_WEn = sdram_we_n
> PORT SDRAM_DQM = sdram_data_mask
> PORT SDRAM_BankAddr = sdram_ba
> PORT SDRAM_Addr = sdram_abus
> PORT SDRAM_DQ = sdram_dbus
> PORT SDRAM_CLK_IN = sys_clk
> PORT PLB_Clk = sys_clk
> END
>
> BEGIN plb2opb_bridge
> PARAMETER INSTANCE = plb2opb
> PARAMETER HW_VER = 1.00.b
> PARAMETER C_NUM_ADDR_RNG = 4
> PARAMETER C_DCR_INTFCE = 0
> PARAMETER C_CLK_ASYNC = 1
> PARAMETER C_RNG0_BASEADDR = 0x60000000
> PARAMETER C_RNG0_HIGHADDR = 0x7FFFFFFF
> PARAMETER C_RNG1_BASEADDR = 0x80000000
> PARAMETER C_RNG1_HIGHADDR = 0xBFFFFFFF
> PARAMETER C_RNG2_BASEADDR = 0xC0000000
> PARAMETER C_RNG2_HIGHADDR = 0xDFFFFFFF
> PARAMETER C_RNG3_BASEADDR = 0xFF000000
> PARAMETER C_RNG3_HIGHADDR = 0xFF1FFFFF
> BUS_INTERFACE SPLB = plb_bus
> BUS_INTERFACE MOPB = opb_bus
> END
>
> BEGIN opb_emc
> PARAMETER INSTANCE = opb_emc_0
> PARAMETER HW_VER = 1.10.b
> PARAMETER C_NUM_BANKS_MEM = 1
> PARAMETER C_DEV_MIR_ENABLE = 0
> PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
> PARAMETER C_SYNCH_MEM_0 = 0
> PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_0 = 60000
> PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 60000
> PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_0 = 60000
> PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_0 = 60000
> PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 60000
> PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_0 = 10000
> PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_0 = 10000
> PARAMETER C_BASEADDR = 0xFF100000
> PARAMETER C_HIGHADDR = 0XFF1001FF
> PARAMETER C_MEM0_BASEADDR = 0xFF00_0000
> PARAMETER C_MEM0_HIGHADDR = 0xFF0F_FFFF
> BUS_INTERFACE SOPB = opb_bus
> PORT Mem_A = sram_addr
> PORT Mem_DQ = sram_data
> PORT Mem_CEN = sram_cen
> PORT Mem_OEN = sram_oen
> PORT Mem_WEN = sram_wen
> PORT Mem_BEN = sram_ben
> PORT Mem_RPN = sram_rst
> END
>
> BEGIN opb_gpio
> PARAMETER INSTANCE = gpio1
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_GPIO_WIDTH = 4
> PARAMETER C_ALL_INPUTS = 0
> PARAMETER C_BASEADDR = 0x90000000
> PARAMETER C_HIGHADDR = 0x900000FF
> BUS_INTERFACE SOPB = opb_bus
> PORT GPIO_IO = gpio
> END
>
> BEGIN opb_intc
> PARAMETER INSTANCE = intc
> PARAMETER HW_VER = 1.00.c
> PARAMETER C_BASEADDR = 0xD0000FC0
> PARAMETER C_HIGHADDR = 0xD0000FDF
> BUS_INTERFACE SOPB = opb_bus
> PORT Irq = interrupt
> PORT Intr = Uart1_intr & sysace_intr & ETH_intr
> END
>
> BEGIN opb_ethernet
> PARAMETER INSTANCE = ethernet
> PARAMETER HW_VER = 1.00.m
> PARAMETER C_DMA_PRESENT = 1
> PARAMETER C_DMA_INTR_COALESCE = 1
> PARAMETER C_OPB_CLK_PERIOD_PS = 10000
> PARAMETER C_BASEADDR = 0x60000000
> PARAMETER C_HIGHADDR = 0x60003FFF
> BUS_INTERFACE MSOPB = opb_bus
> PORT IP2INTC_Irpt = ETH_intr
> PORT Freeze = net_gnd
> PORT PHY_tx_clk = ETH_TXC
> PORT PHY_rx_clk = ETH_RXC
> PORT PHY_crs = ETH_CRS
> PORT PHY_dv = ETH_RXDV
> PORT PHY_rx_data = ETH_RXD
> PORT PHY_col = ETH_COL
> PORT PHY_rx_er = ETH_RXER
> PORT PHY_tx_en = ETH_TXEN
> PORT PHY_tx_er = ETH_TXER
> PORT PHY_tx_data = ETH_TXD
> PORT PHY_Mii_clk = ETH_MDC
> PORT PHY_rst_n = PHY_RESETn
> PORT PHY_Mii_data = ETH_MDIO
> END
>
> BEGIN opb_uart16550
> PARAMETER INSTANCE = uart_16550
> PARAMETER HW_VER = 1.00.c
> PARAMETER C_DEV_BLK_ID = 0
> PARAMETER C_IS_A_16550 = 0
> PARAMETER C_HAS_EXTERNAL_XIN = 0
> PARAMETER C_HAS_EXTERNAL_RCLK = 0
> PARAMETER C_DEV_MIR_ENABLE = 1
> PARAMETER C_BASEADDR = 0xA0000000
> PARAMETER C_HIGHADDR = 0xA0001FFF
> BUS_INTERFACE SOPB = opb_bus
> PORT IP2INTC_Irpt = Uart1_intr
> PORT Freeze = net_gnd
> PORT ctsN = Uart1_ctsN
> PORT dcdN = net_vcc
> PORT dsrN = net_vcc
> PORT riN = net_vcc
> PORT rtsN = Uart1_rtsN
> PORT sin = Uart1_sin
> PORT sout = Uart1_sout
> PORT xin = net_gnd
> PORT rclk = net_gnd
> END
>
> BEGIN opb_sysace
> PARAMETER INSTANCE = sysace
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_BASEADDR = 0xCF000000
> PARAMETER C_HIGHADDR = 0xCF0001FF
> PORT OPB_Clk = sys_clk
> PORT SysACE_CEN = sysace_mpce
> PORT SysACE_CLK = sysace_clk
> PORT SysACE_IRQ = sysace_intr
> PORT SysACE_MPA = sysace_mpa
> PORT SysACE_MPD = sysace_mpd
> PORT SysACE_MPIRQ = sysace_mpirq
> PORT SysACE_OEN = sysace_mpoe
> PORT SysACE_WEN = sysace_mpwe
> BUS_INTERFACE SOPB = opb_bus
> END
>
> BEGIN plb_v34
> PARAMETER INSTANCE = plb_bus
> PARAMETER HW_VER = 1.01.a
> PARAMETER C_DCR_INTFCE = 0
> PORT PLB_Clk = sys_clk
> PORT SYS_Rst = sys_bus_reset
> PORT M_busLock = net_gnd
> END
>
> BEGIN opb_v20
> PARAMETER INSTANCE = opb_bus
> PARAMETER HW_VER = 1.10.a
> PORT OPB_Clk = sys_clk
> PORT SYS_Rst = sys_bus_reset
> END
>
>
>
> ------------------------------------------------------------------------
>
> #
> # XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
> # SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
> # XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
> # AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
> # OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
> # IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
> # AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
> # FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
> # WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
> # IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
> # REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
> # INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
> # FOR A PARTICULAR PURPOSE.
> #
> # (c) Copyright 2002, 2003 Xilinx, Inc.
> # All rights reserved.
> #
> #------------------------------------------------------------------------------
> #
> # Constraints For Virtex II - Pro Design
> #
> #------------------------------------------------------------------------------
>
> #------------------------------------------------------------------------------
> # Timing Ignore Constraints
> #------------------------------------------------------------------------------
> NET system_reset TIG;
> NET c405rstsysresetreq TIG;
> #NET c405rstcoreresetreq TIG;
> #NET c405rstchipresetreq TIG;FF000000
> NET rstc405resetsys TIG;
> #NET rstc405resetchip TIG;
> #NET rstc405resetcore TIG;
> NET c405rstsysresetreq TPTHRU = "RST_GRP";
> #NET c405rstcoreresetreq TPTHRU = "RST_GRP";
> #NET c405rstchipresetreq TPTHRU = "RST_GRP";
> NET rstc405resetsys TPTHRU = "RST_GRP";
> #NET rstc405resetchip TPTHRU = "RST_GRP";
> #NET rstc405resetcore TPTHRU = "RST_GRP";
>
> TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG;
> TIMESPEC "TS_RST2" = FROM FFS THRU RST_GRP TO FFS TIG;
>
> #------------------------------------------------------------------------------
> # Clock Period Constraints
> #------------------------------------------------------------------------------
>
> # 100 MHz Ref Clk to DCM Produces PLB(1X), CPU(1X)
> # (Over-Constrain Period by 100 ps to allow for Jitter, Skew, Noise, Etc)
> NET sys_clk_raw PERIOD = 9.9;
>
> NET sys_clk TNM_NET = "sys_clk";
>
> #------------------------------------------------------------------------------
> # Multicycle Path Constraints
> #------------------------------------------------------------------------------
>
> TIMESPEC "TS_FFS_CPUS" = FROM FFS TO CPUS 9.9 ns;
> TIMESPEC "TS_CPUS_FFS" = FROM CPUS TO FFS 9.9 ns;
>
> #------------------------------------------------------------------------------
> # Generic Catch-All PAD Timing Constraints
> #------------------------------------------------------------------------------
> TIMESPEC "TSOUT" = FROM "FFS" TO "PADS" 9.9 ns;
> TIMESPEC "TSIN" = FROM "PADS" TO "FFS" 9.9 ns;
>
> #------------------------------------------------------------------------------
> # SDRAM PAD Timing Constraints
> #------------------------------------------------------------------------------
> NET sdram_clk FAST ;
>
> #------------------------------------------------------------------------------
> # IO Pad Location Constraints (Memec 2VP7, Rev2 Board)
> #------------------------------------------------------------------------------
> NET sys_clk_raw LOC = D13; # GCLK 1
> NET system_reset LOC = W12;
>
> #------------------------------------------------------------------------------
> # PPC Debug Pad Location Constraints (Memec 2VP7, Rev2 Board)
> #------------------------------------------------------------------------------
> NET cpu_halt LOC = AC12;
> NET cpu_tdo LOC = AA12;
> NET cpu_tdi LOC = AA13;
> NET cpu_tck LOC = Y13;
> NET cpu_tms LOC = W13;
> NET cpu_trst LOC = AD12;
>
> NET cpu_halt PULLUP;
> NET cpu_tdo PULLUP;
> NET cpu_tdi PULLUP;
> NET cpu_tck PULLUP;
> NET cpu_tms PULLUP;
> NET cpu_trst PULLUP;
>
> NET cpu_halt TIG;
> NET cpu_tdo TIG;
> NET cpu_tdi TIG;
> NET cpu_tck TIG;
> NET cpu_tms TIG;
> NET cpu_trst TIG;
>
> #------------------------------------------------------------------------------
> # LED Ports (Active Low)
> #------------------------------------------------------------------------------
>
> NET gpio<0> LOC = D6;
> NET gpio<1> LOC = C6;
> NET gpio<2> LOC = B8;
> NET gpio<3> LOC = B3;
>
> #------------------------------------------------------------------------------
> # Push Buttons (Active Low)
> #------------------------------------------------------------------------------
>
> #NET gpio<4> LOC = E7;
> #NET gpio<5> LOC = A8;
> #NET gpio<6> LOC = A3;
> #NET gpio<7> LOC = ; # unused pin on P7-Rev2 board
>
> #------------------------------------------------------------------------------
> # DIP Switch Ports (Active Low)
> #------------------------------------------------------------------------------
>
> #NET gpio<8> LOC = AD8; # DIP1 (left most)
> #NET gpio<9> LOC = AA8; # DIP2
> #NET gpio<10> LOC = Y9; # DIP3
> #NET gpio<11> LOC = AA9; # DIP4
> #NET gpio<12> LOC = AB8; # DIP5
> #NET gpio<13> LOC = AB9; # DIP6
> #NET gpio<14> LOC = AE8; # DIP7
> #NET gpio<15> LOC = AF8; # DIP8 (right most)
>
> #------------------------------------------------------------------------------
> # LCD Ports
> #------------------------------------------------------------------------------
> #NET lcd_en LOC = F9;
> #NET lcd_rs LOC = G9;
> #NET lcd_data<0> LOC = C12; # LCD.DB7
> #NET lcd_data<1> LOC = D12; # LCD.DB6
> #NET lcd_data<2> LOC = E12; # LCD.DB5
> #NET lcd_data<3> LOC = D7; # LCD.DB4
> #NET lcd_data<4> LOC = F12; # LCD.DB3
> #NET lcd_data<5> LOC = G13; # LCD.DB2
> #NET lcd_data<6> LOC = H13; # LCD.DB1
> #NET lcd_data<7> LOC = H12; # LCD.DB0
>
> #------------------------------------------------------------------------------
> # UART 1 Ports
> #------------------------------------------------------------------------------
> NET Uart1_sin LOC = AB12;
> NET Uart1_rtsN LOC = AC7;
> NET Uart1_ctsN LOC = AC8;
> NET Uart1_sout LOC = AC6;
>
> #------------------------------------------------------------------------------
> # UART 2 Ports
> #------------------------------------------------------------------------------
> #NET Uart2_sin LOC = K26;
> #NET Uart2_rtsN LOC = ;
> #NET Uart2_ctsN LOC = ;
> #NET Uart2_sout LOC = L25;
>
> #------------------------------------------------------------------------------
> # SDRAM Ports
> #------------------------------------------------------------------------------
> NET sdram_abus<11> LOC = R4; # SDARM.A0
> NET sdram_abus<10> LOC = V3; # SDARM.A1
> NET sdram_abus<9> LOC = T4; # SDARM.A2
> NET sdram_abus<8> LOC = T3; # SDARM.A3
> NET sdram_abus<7> LOC = K3; # SDARM.A4
> NET sdram_abus<6> LOC = K4; # SDARM.A5
> NET sdram_abus<5> LOC = N4; # SDARM.A6
> NET sdram_abus<4> LOC = J4; # SDARM.A7
> NET sdram_abus<3> LOC = J3; # SDARM.A8
> NET sdram_abus<2> LOC = L3; # SDARM.A9
> NET sdram_abus<1> LOC = U3; # SDARM.A10
> NET sdram_abus<0> LOC = H4; # SDARM.A11
> NET sdram_dbus<31> LOC = G1;
> NET sdram_dbus<30> LOC = H1;
> NET sdram_dbus<29> LOC = H2;
> NET sdram_dbus<28> LOC = J1;
> NET sdram_dbus<27> LOC = J2;
> NET sdram_dbus<26> LOC = L2;
> NET sdram_dbus<25> LOC = K1;
> NET sdram_dbus<24> LOC = L1;
> NET sdram_dbus<23> LOC = E4;
> NET sdram_dbus<22> LOC = F1;
> NET sdram_dbus<21> LOC = E3;
> NET sdram_dbus<20> LOC = E1;
> NET sdram_dbus<19> LOC = C1;
> NET sdram_dbus<18> LOC = E2;
> NET sdram_dbus<17> LOC = D2;
> NET sdram_dbus<16> LOC = D1;
> NET sdram_dbus<15> LOC = W2;
> NET sdram_dbus<14> LOC = AA1;
> NET sdram_dbus<13> LOC = Y1;
> NET sdram_dbus<12> LOC = AC2;
> NET sdram_dbus<11> LOC = AC1;
> NET sdram_dbus<10> LOC = AD2;
> NET sdram_dbus<9> LOC = AD1;
> NET sdram_dbus<8> LOC = AE1;
> NET sdram_dbus<7> LOC = R1;
> NET sdram_dbus<6> LOC = W1;
> NET sdram_dbus<5> LOC = R2;
> NET sdram_dbus<4> LOC = V2;
> NET sdram_dbus<3> LOC = T1;
> NET sdram_dbus<2> LOC = V1;
> NET sdram_dbus<1> LOC = T2;
> NET sdram_dbus<0> LOC = U1;
> NET sdram_ba<1> LOC = M3;
> NET sdram_ba<0> LOC = W3;
> NET sdram_data_mask<0> LOC = Y5;
> NET sdram_data_mask<2> LOC = G3;
> NET sdram_cs_n LOC = V4;
> NET sdram_ras_n LOC = Y3;
> NET sdram_cas_n LOC = M4;
> NET sdram_we_n LOC = W4;
> NET sdram_clk LOC = G4;
> NET sdram_clk_en LOC = L4;
>
> # SDRAM Byte enable - need to tie these signals to unused pins
> NET sdram_data_mask<1> LOC = AB3;
> NET sdram_data_mask<3> LOC = Y4;
>
>
> # External SRAM Memory Constraints 2VP4 FF672
> #NET "sram_addr<29>" LOC = "R19"; #RIOB32
> #NET "sram_addr<28>" LOC = "AC24"; #RIOA34
> #NET "sram_addr<27>" LOC = "AD23"; #RIOA35
> #NET "sram_addr<26>" LOC = "T20"; #RIOB36
> #NET "sram_addr<25>" LOC = "AB23"; #RIOA33
> #NET "sram_addr<24>" LOC = "AE24"; #RIOA36
> #NET "sram_addr<23>" LOC = "AF24"; #RIOA37
> #NET "sram_addr<22>" LOC = "U20"; #RIOA38
> #NET "sram_addr<21>" LOC = "P25"; #RIOA1
> #NET "sram_addr<20>" LOC = "R25"; #RIOA3
> #NET "sram_addr<19>" LOC = "P22"; #RIOB6
> #NET "sram_addr<18>" LOC = "P20"; #RIOB2
> #NET "sram_addr<17>" LOC = "T26"; #RIOA4
> #NET "sram_addr<16>" LOC = "T25"; #RIOA5
> #NET "sram_addr<15>" LOC = "V25"; #RIOA8
> #NET "sram_addr<14>" LOC = "P21"; #RIOB4
> #NET "sram_addr<13>" LOC = "R22"; #RIOB8
> #NET "sram_addr<12>" LOC = "T21"; #RIOB34
> #NET "sram_addr<11>" LOC = "U21"; #RIOB38
> #NET "sram_addr<10>" LOC = "R26"; #RIOA2
> #NET "sram_data<31>" LOC = "AF25"; #RIOA18
> #NET "sram_data<30>" LOC = "R24"; #RIOA21
> #NET "sram_data<29>" LOC = "AE26"; #RIOA17
> #NET "sram_data<28>" LOC = "V22"; #RIOB14
> #NET "sram_data<27>" LOC = "AC26"; #RIOA13
> #NET "sram_data<26>" LOC = "AC25"; #RIOA14
> #NET "sram_data<25>" LOC = "W26"; #RIOA9
> #NET "sram_data<24>" LOC = "Y26"; #RIOA11
> #NET "sram_data<23>" LOC = "Y22"; #RIOB18
> #NET "sram_data<22>" LOC = "AD25"; #RIOA16
> #NET "sram_data<21>" LOC = "W22"; #RIOB16
> #NET "sram_data<20>" LOC = "AD26"; #RIOA15
> #NET "sram_data<19>" LOC = "AA26"; #RIOA12
> #NET "sram_data<18>" LOC = "T22"; #RIOB10
> #NET "sram_data<17>" LOC = "U22"; #RIOB12
> #NET "sram_data<16>" LOC = "W25"; #RIOA10
> #NET "sram_data<15>" LOC = "R21"; #RIOB30
> #NET "sram_data<14>" LOC = "AB24"; #RIOA32
> #NET "sram_data<13>" LOC = "R20"; #RIOB28
> #NET "sram_data<12>" LOC = "V24"; #RIOA27
> #NET "sram_data<11>" LOC = "P19"; #RIOB26
> #NET "sram_data<10>" LOC = "U23"; #RIOA26
> #NET "sram_data<9>" LOC = "R23"; #RIOA22
> #NET "sram_data<8>" LOC = "T24"; #RIOA23
> #NET "sram_data<7>" LOC = "W23"; #RIOA30
> #NET "sram_data<6>" LOC = "Y24"; #RIOA31
> #NET "sram_data<5>" LOC = "W24"; #RIOA29
> #NET "sram_data<4>" LOC = "V23"; #RIOA28
> #NET "sram_data<3>" LOC = "U24"; #RIOA25
> #NET "sram_data<2>" LOC = "T23"; #RIOA24
> #NET "sram_data<1>" LOC = "T19"; #RIOB24
> #NET "sram_data<0>" LOC = "Y21"; #RIOB22
> #NET "sram_cen<0>" LOC = "P23"; #RIOA20
> #NET "sram_wen" LOC = "Y23"; #RIOA40
> #NET "sram_oen" LOC = "P24"; #RIOA19
> #NET "sram_ben<0>" LOC = "J21"; #LIOA27
> #NET "sram_ben<1>" LOC = "J22"; #LIOA25
> #NET "sram_ben<2>" LOC = "L24"; #LIOB27
> #NET "sram_ben<3>" LOC = "A25"; #LIOB26
> #NET "sram_rst" LOC = "E24"; #LIOB37
> #NET "sram_cefn" LOC = "W21"; #RIOB20
>
> #------------------------------------------------------------------------------
> # Ethernet Ports
> #------------------------------------------------------------------------------
> NET "ETH_TXC" LOC = "E20"; #LIOA35(.2v5)
> NET "ETH_RXC" LOC = "D21"; #LIOA33(.2v5
> NET "ETH_CRS" LOC = "B26"; #LIOB25
> NET "ETH_RXDV" LOC = "C19"; #LIOA17(.2v5)
> NET "ETH_RXD<0>" LOC = "G26"; #LIOB17
> NET "ETH_RXD<1>" LOC = "H25"; #LIOB16
> #NET "ETH_RXD<2>" LOC = "G20"; #LIOA15 Rev1 board
> NET "ETH_RXD<2>" LOC = "E14"; #Rev2 board
> NET "ETH_RXD<3>" LOC = "AC14"; #LIOB15
> NET "ETH_COL" LOC = "C25"; #LIOB24
> NET "ETH_RXER" LOC = "E26"; #LIOB19
> NET "ETH_TXEN" LOC = "D26"; #LIOB21
> NET "ETH_TXER" LOC = "D19"; #LIOA19(.2v5)
> NET "ETH_TXD<0>" LOC = "D20"; #LIOA21(.2v5)
> NET "ETH_TXD<1>" LOC = "D25"; #LIOB22
> NET "ETH_TXD<2>" LOC = "C26"; #LIOB23
> NET "ETH_TXD<3>" LOC = "C21"; #LIOA23(.2v5)
> NET "ETH_MDC" LOC = "J25"; #LIOB14
> NET "PHY_RESETn" LOC = "J24"; #LIOB31
> #NET "ETH_MDIO" LOC = "H19"; #LIOA13 Rev 1 board
> NET "ETH_MDIO" LOC = "D14"; #LIOA13 Rev 2 board
>
> #------------------------------------------------------------------------------
> # IO Pad Location Constraints / Properties for System ACE MPU Controller
> #------------------------------------------------------------------------------
>
> NET sysace_clk LOC = E13;
> NET sysace_clk TNM_NET = "sysace_clk";
> ## Leave 1 ns margin
> TIMESPEC "TSSYSACE" = PERIOD "sysace_clk" 29 ns;
>
> NET sysace_mpa<0> LOC = R19;
> NET sysace_mpa<1> LOC = AC24;
> NET sysace_mpa<2> LOC = AD23;
> NET sysace_mpa<3> LOC = T20;
> NET sysace_mpa<4> LOC = AB23;
> NET sysace_mpa<5> LOC = AE24;
> NET sysace_mpa<6> LOC = AF24;
>
> NET sysace_mpce LOC = F26;
>
> NET sysace_mpd<0> LOC = W25;
> NET sysace_mpd<1> LOC = U22;
> NET sysace_mpd<2> LOC = T22;
> NET sysace_mpd<3> LOC = AA26;
> NET sysace_mpd<4> LOC = AD26;
> NET sysace_mpd<5> LOC = W22;
> NET sysace_mpd<6> LOC = AD25;
> NET sysace_mpd<7> LOC = Y22;
>
> NET sysace_mpoe LOC = P24;
> NET sysace_mpwe LOC = Y23;
> NET sysace_mpirq LOC = E25;
> NET sysace_mpirq TIG;
>
>
>
> ## Timing ignores (to specify unconstrained paths)
> TIMESPEC "TS_SYSACE_OPB" = FROM "sysace_clk" TO "sys_clk" TIG;
> TIMESPEC "TS_OPB_SYSACE" = FROM "sys_clk" TO "sysace_clk" TIG;
>
--
Dr John Williams, Research Fellow,
Reconfigurable Computing, School of ITEE
University of Queensland, Brisbane, Australia
Ph : (07) 3365 8305
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