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[microblaze-uclinux] More details of my problem - uClinux freezes too
Hi,
i don't know what it is the problem yet, i try to configure mi platform
similar to mbvanilla, but the output is the same:
Linux version 2.4.24-uc0 (ivan@medea) (gcc version 2.95.3-4 Xilinx EDK
6.1 Bui4On node 0 totalpages: 5Bc
zone(0): 5Bc pages.
zone(1): 0 pages.
zone(2): 0 pages.
CPU: MICROBLAZE
Console: xmbserial on UARTLite
Kernel command line:
The execution stops in function kmem_cache_estimate(), in
uClinux-2.4.x/mmnommu/slab.c. I think that the line "zone(0): 5Bc pages"
would be "zone(0): 512 pages", because 2 MB/4906 = 512 (in mbvanilla
case, this value is 16 MB/4096 = 4096) ¿don't it?
i try to execute the image.bin in demo package, but the output is
similar to the previous one:
Linux version 2.4.21-uc0 (jwilliam@g435-9029) (gcc version 2.95.3-4
Xilinx EDK3On node 0 totalpages: 40 zone(0): 0 pages.
zone(1): 40 zone(2): 0 pages.
CPU: MICROBLAZE
Console: xmbserial on UARTLite
Kernel command line:
In default kernel settings the cache is not used, so the problem can not
be the cache (i don't use it in the platform configuration too) ¿?
Well, this is the changes that i did in uClinux sources:
Index: arch/microblaze/mbvanilla.ld
===================================================================
RCS file: /var/cvs/uClinux-2.4.x/arch/microblaze/mbvanilla.ld,v
retrieving revision 1.7
diff -u -r1.7 mbvanilla.ld
--- arch/microblaze/mbvanilla.ld 2003/09/22 04:34:24 1.7
+++ arch/microblaze/mbvanilla.ld 2004/02/29 21:17:31
@@ -15,8 +15,8 @@
/* 1MB of OPB SRAM */
/* OPB : ORIGIN = 0xFFE00000, LENGTH = 0x00100000 */
- /* 16 MB of OBP SDRAM */
- OPB : ORIGIN = 0x80000000, LENGTH = 0x01000000
+ /* 2 MB of OBP SDRAM */
+ OPB : ORIGIN = 0x80000000, LENGTH = 0x00200000
}
SECTIONS {
Index: include/asm-microblaze/mbvanilla.h
===================================================================
RCS file: /var/cvs/uClinux-2.4.x/include/asm-microblaze/mbvanilla.h,v
retrieving revision 1.4
diff -u -r1.4 mbvanilla.h
--- include/asm-microblaze/mbvanilla.h 2003/08/12 01:55:07 1.4
+++ include/asm-microblaze/mbvanilla.h 2004/02/29 21:17:34
@@ -47,14 +47,14 @@
/* GPIO */
#ifndef MICROBLAZE_GPIO_BASE_ADDR
#define MICROBLAZE_GPIO_BASE_ADDR 0xFFFF5000
-#define MICROBLAZE_GPIO_DIR 0x0000FF00
+#define MICROBLAZE_GPIO_DIR 0x00000000 // all outputs
#endif
/* Start and size of external RAM */
/* #define ERAM_ADDR 0xFFE00000
#define ERAM_SIZE 0x00100000 */
#define ERAM_ADDR 0x80000000
-#define ERAM_SIZE 0x01000000
+#define ERAM_SIZE 0x00200000
/* for <asm/page.h> */
#define PAGE_OFFSET ERAM_ADDR
Index: include/asm-microblaze/microblaze_gpio.h
===================================================================
RCS file:
/var/cvs/uClinux-2.4.x/include/asm-microblaze/microblaze_gpio.h,v
retrieving revision 1.1
diff -u -r1.1 microblaze_gpio.h
--- include/asm-microblaze/microblaze_gpio.h 2003/04/02 05:07:16
1.1
+++ include/asm-microblaze/microblaze_gpio.h 2004/02/29 21:17:34
@@ -8,7 +8,7 @@
* 0 configures pin for output and 1 for input.
*/
#define MICROBLAZE_GPIO_DATA_OFFSET 0x00000000
-#define MICROBLAZE_GPIO_TRI_OFFSET 0x00000004
+#define MICROBLAZE_GPIO_TRI_OFFSET 0x00000000 // all outputs
#define microblaze_gpio_setdir(BaseAddress, Data) \
*((unsigned int *)(BaseAddress+MICROBLAZE_GPIO_TRI_OFFSET)) =
(unsigned int)Data
Index: include/asm-microblaze/xparameters.h
===================================================================
RCS file: /var/cvs/uClinux-2.4.x/include/asm-microblaze/xparameters.h,v
retrieving revision 1.4
diff -u -r1.4 xparameters.h
--- include/asm-microblaze/xparameters.h 2003/11/28 05:11:31
1.4
+++ include/asm-microblaze/xparameters.h 2004/02/29 21:17:35
@@ -2,7 +2,7 @@
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
-* Version: Xilinx EDK 3.2.2 EDK_Cm.22
+* Version: Xilinx EDK 6.1 EDK_G.12
* DO NOT EDIT.
*
* Copyright (c) 2003 Xilinx, Inc. All rights reserved.
@@ -15,10 +15,6 @@
#define XPAR_D_LMB_BRAM_IF_CNTLR_HIGHADDR 0x00003FFF
#define XPAR_I_LMB_BRAM_IF_CNTLR_BASEADDR 0x00000000
#define XPAR_I_LMB_BRAM_IF_CNTLR_HIGHADDR 0x00003FFF
-#define XPAR_DDR_CONTROLLER_BASEADDR 0x80000000
-#define XPAR_DDR_CONTROLLER_HIGHADDR 0x80FFFFFF
-#define XPAR_SYSTEM_MEMCON_BASEADDR 0xFFFF0000
-#define XPAR_SYSTEM_MEMCON_HIGHADDR 0xFFFF00FF
/******************************************************************/
@@ -33,11 +29,11 @@
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 3
#define XPAR_INTC_SINGLE_BASEADDR 0xFFFF3000
#define XPAR_INTC_SINGLE_HIGHADDR 0xFFFF30FF
-#define XPAR_XINTC_NUM_INSTANCES 1
#define XPAR_XINTC_USE_DCR 0
+#define XPAR_XINTC_NUM_INSTANCES 1
#define XPAR_SYSTEM_INTC_BASEADDR 0xFFFF3000
#define XPAR_SYSTEM_INTC_HIGHADDR 0xFFFF30FF
-#define XPAR_SYSTEM_INTC_KIND_OF_INTR 0x0000006E
+#define XPAR_SYSTEM_INTC_KIND_OF_INTR 0x00000006
/******************************************************************/
@@ -53,40 +49,29 @@
/******************************************************************/
-#define XPAR_XGPIO_NUM_INSTANCES 1
+#define XPAR_XGPIO_NUM_INSTANCES 3
#define XPAR_SYSTEM_GPIO_BASEADDR 0xFFFF5000
#define XPAR_SYSTEM_GPIO_HIGHADDR 0xFFFF50FF
#define XPAR_SYSTEM_GPIO_DEVICE_ID 0
+#define XPAR_GPIO_MEM_REQ_BASEADDR 0xFFFF0400
+#define XPAR_GPIO_MEM_REQ_HIGHADDR 0xFFFF04FF
+#define XPAR_GPIO_MEM_REQ_DEVICE_ID 1
+#define XPAR_GPIO_MEM_GNT_BASEADDR 0xFFFF0500
+#define XPAR_GPIO_MEM_GNT_HIGHADDR 0xFFFF05FF
+#define XPAR_GPIO_MEM_GNT_DEVICE_ID 2
#define XPAR_GPIO_0_BASEADDR XPAR_SYSTEM_GPIO_BASEADDR
#define XPAR_GPIO_0_HIGHADDR XPAR_SYSTEM_GPIO_HIGHADDR
#define XPAR_GPIO_0_DEVICE_ID XPAR_SYSTEM_GPIO_DEVICE_ID
/******************************************************************/
-
-#define XPAR_XEMAC_NUM_INSTANCES 1
-#define XPAR_EMAC_0_BASEADDR 0xC0000000
-#define XPAR_EMAC_0_HIGHADDR 0xC0003FFF
-#define XPAR_EMAC_0_DEVICE_ID 0
-
-#define XPAR_OPB_ETHERNET_0_DEVICE_ID XPAR_EMAC_0_DEVICE_ID
-#define XPAR_OPB_ETHERNET_0_BASEADDR XPAR_EMAC_0_BASEADDR
-
-#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
-#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
-#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
-
-/******************************************************************/
-#define XPAR_XSYSACE_NUM_INSTANCES 1
-#define XPAR_SYSACE_0_HIGHADDR 0xCF0001FF
-#define XPAR_SYSACE_0_BASEADDR 0xCF000000
-#define XPAR_OPB_SYSACE_0_DEVICE_ID 0
-#define XPAR_OPB_SYSACE_0_BASEADDR XPAR_SYSACE_0_BASEADDR
+#define XPAR_XFLASH_NUM_INSTANCES 1
+#define XPAR_SYSTEM_MEMCON_BASEADDR 0xFFFF0000
+#define XPAR_SYSTEM_MEMCON_HIGHADDR 0xFFFF00FF
/******************************************************************/
#define STDIN_BASEADDRESS 0xFFFF2000
#define STDOUT_BASEADDRESS 0xFFFF2000
-
extern void XIntc_LowLevelInterruptHandler(void) __attribute__
((interrupt_handler));
¿Any idea? I'm lost...
Ivan
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