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Re: [microblaze-uclinux] More details of my problem - uClinux freezes too
Hello John and Yasushi,
i try to answer yours questions:
------------ Yasushi -----------------
>> Linux version 2.4.24-uc0 (yashi@wat) (gcc version
>> 2.95.3-4 Xilinx EDK 6.1 Build EDK_G.11) #197 Mon
Mar
>> 1 08:50:17 JST 2004
>> On node 0 totalpages: 512
Opps, :)
>> can you put printk in kmem_cache_estimate() to see
>> exactly where the kernel stoped?
Yes, in line 443 of slab.c file:
while (i*size + L1_CACHE_ALIGN(base+i*extra) <=
wastage) i++;
------------- John ---------------------
>> My recommendation is to
>> (a) post your .mhs file to the list for us to have
a
>> closer look.
# Parameters
PARAMETER VERSION = 2.1.0
PORT sys_clk = sys_clk, DIR = I, SIGIS = CLK
PORT console_uart_rx = console_uart_rx, DIR = I
PORT console_uart_tx = console_uart_tx, DIR = O
PORT debug_uart_rx = debug_uart_rx, DIR = I
PORT debug_uart_tx = debug_uart_tx, DIR = O
PORT gpio = gpio, VEC = [0:7], DIR = IO
PORT sram_addr = sram_addr, VEC = [0:31], DIR = O
PORT sram_data = sram_data, VEC = [31:0], DIR = IO
PORT sram_oen = sram_oen, DIR = O
PORT sram_wen = sram_wen, DIR = O
PORT sram_cen = sram_cen, VEC = [0:3], DIR = O
PORT mem_req = mem_req, VEC = [0:1], DIR = IO
PORT mem_gnt = mem_gnt, VEC = [0:1], DIR = IO
PORT sys_rst = sys_rst, DIR = I
# log2(cacheable_range) = log2(cache_size) + tag_bits
# tag_bits = log2(2MB)-log2(16384)
# tag_bits = 21-14 = 7
# Sub Components
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_USE_DIV = 1
PARAMETER C_USE_BARREL = 1
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 2
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 2
PARAMETER C_USE_ICACHE = 1
PARAMETER C_ICACHE_BASEADDR = 0x80000000
PARAMETER C_ICACHE_HIGHADDR = 0x801FFFFF
PARAMETER C_CACHE_BYTE_SIZE = 16384
PARAMETER C_ADDR_TAG_BITS = 7
PARAMETER C_USE_DCACHE = 1
PARAMETER C_DCACHE_BASEADDR = 0x80000000
PARAMETER C_DCACHE_HIGHADDR = 0x801FFFFF
PARAMETER C_DCACHE_BYTE_SIZE = 16384
PARAMETER C_DCACHE_ADDR_TAG = 7
BUS_INTERFACE DLMB = d_lmb_v10
BUS_INTERFACE ILMB = i_lmb_v10
BUS_INTERFACE DOPB = d_opb_v20
BUS_INTERFACE IOPB = d_opb_v20
PORT CLK = sys_clk
PORT INTERRUPT = interrupt
END
BEGIN opb_uartlite
PARAMETER INSTANCE = console_uart
PARAMETER HW_VER = 1.00.b
PARAMETER C_CLK_FREQ = 50_000_000
PARAMETER C_BAUDRATE = 57600
PARAMETER C_DATA_BITS = 8
PARAMETER C_USE_PARITY = 0
PARAMETER C_BASEADDR = 0xFFFF2000
PARAMETER C_HIGHADDR = 0xFFFF20FF
BUS_INTERFACE SOPB = d_opb_v20
PORT Interrupt = console_uart_interrupt
PORT OPB_Clk = sys_clk
PORT RX = console_uart_rx
PORT TX = console_uart_tx
END
BEGIN opb_uartlite
PARAMETER INSTANCE = debug_uart
PARAMETER HW_VER = 1.00.b
PARAMETER C_CLK_FREQ = 50_000_000
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_USE_PARITY = 0
PARAMETER C_BASEADDR = 0xFFFF4000
PARAMETER C_HIGHADDR = 0xFFFF40FF
BUS_INTERFACE SOPB = d_opb_v20
PORT Interrupt = debug_uart_interrupt
PORT OPB_Clk = sys_clk
PORT RX = debug_uart_rx
PORT TX = debug_uart_tx
END
BEGIN opb_intc
PARAMETER INSTANCE = system_intc
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0xffff3000
PARAMETER C_HIGHADDR = 0xffff30ff
BUS_INTERFACE SOPB = d_opb_v20
PORT Irq = interrupt
PORT OPB_Clk = sys_clk
PORT Intr = debug_uart_interrupt &
console_uart_interrupt & timer_interrupt
END
BEGIN opb_timer
PARAMETER INSTANCE = system_timer
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0xffff1000
PARAMETER C_HIGHADDR = 0xffff10ff
BUS_INTERFACE SOPB = d_opb_v20
PORT OPB_Clk = sys_clk
PORT Interrupt = timer_interrupt
END
BEGIN opb_gpio
PARAMETER INSTANCE = system_gpio
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0xffff5000
PARAMETER C_HIGHADDR = 0xffff50ff
PARAMETER C_GPIO_WIDTH = 8
BUS_INTERFACE SOPB = d_opb_v20
PORT GPIO_IO = gpio
PORT OPB_Clk = sys_clk
END
BEGIN opb_emc
PARAMETER INSTANCE = system_memcon
PARAMETER HW_VER = 1.10.b
PARAMETER C_BASEADDR = 0xFFFF0000
PARAMETER C_HIGHADDR = 0xFFFF00FF
PARAMETER C_OPB_CLK_PERIOD_PS = 20000
PARAMETER C_MEM0_BASEADDR = 0x80000000
PARAMETER C_MEM0_HIGHADDR = 0x801FFFFF
PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_0 = 15000
PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_0 = 15000
PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 15000
PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 15000
PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_0 = 10000
BUS_INTERFACE SOPB = d_opb_v20
PORT OPB_Clk = sys_clk
PORT Mem_A = sram_addr
PORT Mem_DQ = sram_data
PORT Mem_OEN = sram_oen
PORT Mem_WEN = sram_wen
PORT Mem_BEN = sram_cen
END
BEGIN opb_mdm
PARAMETER INSTANCE = mdm
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0xffff7000
PARAMETER C_HIGHADDR = 0xffff70ff
BUS_INTERFACE SOPB = d_opb_v20
PORT OPB_Clk = sys_clk
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = d_lmb_bram_if_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003FFF
BUS_INTERFACE SLMB = d_lmb_v10
BUS_INTERFACE BRAM_PORT = conn_0
PORT LMB_Clk = sys_clk
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = i_lmb_bram_if_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003FFF
BUS_INTERFACE SLMB = i_lmb_v10
BUS_INTERFACE BRAM_PORT = conn_1
PORT LMB_Clk = sys_clk
END
BEGIN bram_block
PARAMETER INSTANCE = bram
PARAMETER HW_VER = 1.00.a
PARAMETER C_MEMSIZE = 16384
BUS_INTERFACE PORTA = conn_0
BUS_INTERFACE PORTB = conn_1
END
BEGIN opb_v20
PARAMETER INSTANCE = d_opb_v20
PARAMETER HW_VER = 1.10.b
PARAMETER C_EXT_RESET_HIGH = 0
PORT OPB_Clk = sys_clk
PORT SYS_Rst = sys_rst
END
BEGIN lmb_v10
PARAMETER INSTANCE = i_lmb_v10
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT LMB_Clk = sys_clk
PORT SYS_Rst = sys_rst
END
BEGIN lmb_v10
PARAMETER INSTANCE = d_lmb_v10
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT LMB_Clk = sys_clk
PORT SYS_Rst = sys_rst
END
### This gpio is for DMA Arbitrer, to request the SRAM
### memory (is controlled by the bootloader)
BEGIN opb_gpio
PARAMETER INSTANCE = gpio_mem_req
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0xFFFF0400
PARAMETER C_HIGHADDR = 0xFFFF04FF
PARAMETER C_GPIO_WIDTH = 2
BUS_INTERFACE SOPB = d_opb_v20
PORT OPB_Clk = sys_clk
PORT GPIO_IO = mem_req
END
BEGIN opb_gpio
PARAMETER INSTANCE = gpio_mem_gnt
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0xFFFF0500
PARAMETER C_HIGHADDR = 0xFFFF05FF
PARAMETER C_GPIO_WIDTH = 2
BUS_INTERFACE SOPB = d_opb_v20
PORT OPB_Clk = sys_clk
PORT GPIO_IO = mem_gnt
END
This two last gpio are controlled by the bootloader
program (in LMB memory) to request the memory, because
the SRAM memory is shared between the host and FPGA
throw a DMA Arbitrer.
I use a opb_emc to managed the SRAM memory (the memcon
is deprecated). Also, i don't have DDR Memory.
>> (b) revert your uClinux-2.4.x source tree back to
the CVS "standard"
Ok
>> (c) take the existing mbvanilla platform, and make
>> the absolute minimal changes necessary to make it
>> work on your board. Test it first by writing
simple
>> microblaze programs that spits stuff out on the
>> serial port, toggles the LEDs, that sort of thing.
I hope that my changes was minimal :)
I had executed several programs with this hardware
configuration as: a image des/IDEA cipher program,
etc... an all work ok.
>> (d) make the bare minimum changes in the kernel
tree
>> to match your hardware platform.
These are the actual changes that i done following
your instructions (but the result is the same):
Index: arch/microblaze/mbvanilla.ld
===================================================================
RCS file:
/var/cvs/uClinux-2.4.x/arch/microblaze/mbvanilla.ld,v
retrieving revision 1.7
diff -u -r1.7 mbvanilla.ld
--- arch/microblaze/mbvanilla.ld 2003/09/22 04:34:24
1.7
+++ arch/microblaze/mbvanilla.ld 2004/03/01 14:15:22
@@ -15,8 +15,8 @@
/* 1MB of OPB SRAM */
/* OPB : ORIGIN = 0xFFE00000, LENGTH = 0x00100000
*/
- /* 16 MB of OBP SDRAM */
- OPB : ORIGIN = 0x80000000, LENGTH = 0x01000000
+ /* 2 MB of OBP SDRAM */
+ OPB : ORIGIN = 0x80000000, LENGTH = 0x00200000
}
SECTIONS {
Index: include/asm-microblaze/mbvanilla.h
===================================================================
RCS file:
/var/cvs/uClinux-2.4.x/include/asm-microblaze/mbvanilla.h,v
retrieving revision 1.4
diff -u -r1.4 mbvanilla.h
--- include/asm-microblaze/mbvanilla.h 2003/08/12
01:55:07 1.4
+++ include/asm-microblaze/mbvanilla.h 2004/03/01
14:15:32
@@ -54,7 +54,7 @@
/* #define ERAM_ADDR 0xFFE00000
#define ERAM_SIZE 0x00100000 */
#define ERAM_ADDR 0x80000000
-#define ERAM_SIZE 0x01000000
+#define ERAM_SIZE 0x00200000
/* for <asm/page.h> */
#define PAGE_OFFSET ERAM_ADDR
---------------
Another important thing is that i work in EXECUTABLE
mode to init the BRAM memory with a bootloader program
(based on the bootloader implemented by John in the
bootloader.c file). I load all programs in srec format
with this bootloader throw serial port and all works
fine. And, obviously, i load the image.srec using this
method.
Best regards,
Ivan
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