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AW: [microblaze-uclinux] OT?, Performance
Hi Everybody here at this list, i am new to this mailing list but not to
fpga design. so here are some comments from my side ...
why intergrating as much as possible ?
every hw designer might face that problem .. you have done a design, you
have finished it, it runs under full production and then the manufacture of
that cpu suddenly stops the production and make the device obsolete ... have
been through that quite often. so the only protection against that ist
having the "devices" as ip cores or much better having the sources of that
core. so you are save for quite a much longer time no one can make your
design obsolete ...
next reason ... emc and all this stuff ... that is a point most sw engineers
do not take into account that every physical connection acts as an antennae
and pollutes the enviroment. The transmitted energy of a certain frequency
is proportional to frequency^4. that means the higher frequency the higher
(by the power of 4) the emitted "signal" or noise is. so the only
possability here is to make the trace length as short as possible. shortest
solution is having it on one chip (fpga) to integrate as much as possible.
(also reducing pin count but i gues you are all aware of that)...
so if the design in a fpga is a 100% synchronous design, the only thing that
limits the speed is the fpga and the design that runs in it.
About c source to fpga ... a while ago a company presented us a tool which
was able to convert pure c source into verilog hdl. they have presented us a
demonstration where a complexe animated 3d figures with raytracing and live
videostreams coming from a webcam where dislpayed on a normal video beamer.
everybody who has done 3d animated raytracing knows what performace is
neseccary for that, but the wohle c source was translated, synth. and runs
on a spartan with a external clock speed of 25MHz .... amazing.
so this was a realy realy good demonstration how pure software can be
translated in gates and do real paralell calculations.
making things in fpga gates or software is mostly a matter of the target
application. we will as much as possible in hdl if the selected fpga has
enough gates left (we have payed for each gate in that fpga so we use it).
so the performance is importand because we have to compare the
cpucost_per_fpga / DMIPS and Watts / DMIPS with external solutions. so i
guess there are a lot of other mailinglist readers like me that just read,
listen what others have to say about microblaze in addition to uClinux. and
performace IS a important thing.
so thanks for the DMIPS information regarding microblaze with uCLinux.
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