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Re: [microblaze-uclinux] Porting help

To: aurash <microblaze-uclinux@xxxxxxxxxxxxxx>
Subject: Re: [microblaze-uclinux] Porting help
From: Richard Klosinski <rklosinski@xxxxxxxxxxxxx>
Date: Wed, 6 Oct 2004 14:32:56 -0700
Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxx
I dont know. I got the .mhs section from creating a new project using project studio for the nuhorizon board (using base system builder). I would assume it worked. Why do I need to reverse the address lines? 

Anyway, I have modified the heartbeat routine in mbvanilla to just toggle the state of the output pin, and i get the led's blinking at 1x a second. so something is working. Oldly, the heartbeat does not blink using the stock code. However the parameter 'value' is passed to it, it must not be changing.

During the boot process, I see a few printk message being executed, but none ever appear on my terminal. I verified operation of the ports outside of linux.

Rich


Original Message -----------------------
Richard,
Did you reversed the external address bus?
for instance the A11 pin from the memory should be connected with the A0 
on the memory controller (swap in the  system.ucf file)

Aurash

Richard Klosinski wrote:

>Ram testing consisted of an alternating patterns in memory for bus testing,
>then walking 1x17 for address testing. Seems to be all there. Anyway, here
>is the mhs
>
>#
>############################################################################
># Target Board:	 NuHorizon Spartan 3 Development Board
># Family:	     Spartan
># Device:	     XC3S400
># Package:
># Speed Grade:	 -4
># Processor:     Microblaze
># Debug interface: On-Chip HW Debug Module
># On Chip Memory :   16 KB
># Total Off Chip Memory :  8 MB
># - SDRAM_4Mx16 =  8 MB
>#
>############################################################################
># Parameters
> PARAMETER VERSION = 2.1.0
>
>
># Global Ports
> PORT console_uart_rx = console_uart_rx, DIR = IN
> PORT console_uart_tx = console_uart_tx, DIR = OUT
> PORT debug_uart_rx = debug_uart_rx, DIR = IN
> PORT debug_uart_tx = debug_uart_tx, DIR = OUT
> PORT gpio = gpio, DIR = INOUT, VEC = [0:7]
> PORT SDRAM_4Mx16_SDRAM_WEn = SDRAM_4Mx16_SDRAM_WEn, DIR = OUT
> PORT SDRAM_4Mx16_SDRAM_CKE = SDRAM_4Mx16_SDRAM_CKE, DIR = OUT
> PORT SDRAM_4Mx16_SDRAM_CSn = SDRAM_4Mx16_SDRAM_CSn, DIR = OUT
> PORT SDRAM_4Mx16_SDRAM_CASn = SDRAM_4Mx16_SDRAM_CASn, DIR = OUT
> PORT SDRAM_4Mx16_SDRAM_RASn = SDRAM_4Mx16_SDRAM_RASn, DIR = OUT
> PORT SDRAM_4Mx16_SDRAM_Clk = SDRAM_4Mx16_SDRAM_Clk, DIR = OUT
> PORT SDRAM_4Mx16_SDRAM_Addr = SDRAM_4Mx16_SDRAM_Addr, DIR = OUT, VEC =
>[0:11]
> PORT SDRAM_4Mx16_SDRAM_BankAddr = SDRAM_4Mx16_SDRAM_BankAddr, DIR = OUT,
>VEC = [0:1]
> PORT SDRAM_4Mx16_SDRAM_DQ = SDRAM_4Mx16_SDRAM_DQ, DIR = INOUT, VEC = [0:15]
> PORT sys_clk = sys_clk, DIR = IN, SIGIS = CLK
> PORT sys_rst = sys_rst, DIR = IN
> PORT Ethernet_MAC_PHY_tx_er = Ethernet_MAC_PHY_tx_er, DIR = OUT
> PORT Ethernet_MAC_PHY_tx_clk = Ethernet_MAC_PHY_tx_clk, DIR = IN
> PORT Ethernet_MAC_PHY_rx_clk = Ethernet_MAC_PHY_rx_clk, DIR = IN
> PORT Ethernet_MAC_PHY_crs = Ethernet_MAC_PHY_crs, DIR = IN
> PORT Ethernet_MAC_PHY_dv = Ethernet_MAC_PHY_dv, DIR = IN
> PORT Ethernet_MAC_PHY_col = Ethernet_MAC_PHY_col, DIR = IN
> PORT Ethernet_MAC_PHY_rx_er = Ethernet_MAC_PHY_rx_er, DIR = IN
> PORT Ethernet_MAC_PHY_tx_en = Ethernet_MAC_PHY_tx_en, DIR = OUT
> PORT Ethernet_MAC_PHY_Mii_clk = Ethernet_MAC_PHY_Mii_clk, DIR = INOUT
> PORT Ethernet_MAC_PHY_rst_n = Ethernet_MAC_PHY_rst_n, DIR = OUT
> PORT Ethernet_MAC_PHY_Mii_data = Ethernet_MAC_PHY_Mii_data, DIR = INOUT
> PORT Ethernet_MAC_PHY_rx_data = Ethernet_MAC_PHY_rx_data, DIR = IN, VEC =
>[3:0]
> PORT Ethernet_MAC_PHY_tx_data = Ethernet_MAC_PHY_tx_data, DIR = OUT, VEC =
>[3:0]
>
>
># Sub Components
>BEGIN microblaze
> PARAMETER INSTANCE = microblaze_0
> PARAMETER HW_VER = 2.10.a
> PARAMETER C_USE_BARREL = 1
> PARAMETER C_USE_DIV = 1
> PARAMETER C_DEBUG_ENABLED = 1
> PARAMETER C_NUMBER_OF_PC_BRK = 4
> PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
> PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
># PARAMETER C_USE_ICACHE = 1
># PARAMETER C_ICACHE_BASEADDR = 0x80000000
># PARAMETER C_ICACHE_HIGHADDR = 0x81FFFFFF
># PARAMETER C_CACHE_BYTE_SIZE = 16384
># PARAMETER C_ADDR_TAG_BITS = 11
># PARAMETER C_USE_DCACHE = 1
># PARAMETER C_DCACHE_BASEADDR = 0x80000000
># PARAMETER C_DCACHE_HIGHADDR = 0x81FFFFFF
># PARAMETER C_DCACHE_BYTE_SIZE = 16384
># PARAMETER C_DCACHE_ADDR_TAG = 11
> PARAMETER C_FSL_LINKS = 1
> BUS_INTERFACE SFSL0 = download_link
> BUS_INTERFACE DLMB = d_lmb_v10
> BUS_INTERFACE ILMB = i_lmb_v10
> BUS_INTERFACE DOPB = d_opb_v20
> BUS_INTERFACE IOPB = d_opb_v20
> PORT CLK = sys_clk
> PORT INTERRUPT = interrupt
>END
>
>BEGIN opb_mdm
> PARAMETER INSTANCE = debug_module
> PARAMETER HW_VER = 2.00.a
> PARAMETER C_MB_DBG_PORTS = 1
> PARAMETER C_USE_UART = 1
> PARAMETER C_UART_WIDTH = 8
> PARAMETER C_BASEADDR = 0xFFFFC000
> PARAMETER C_HIGHADDR = 0xFFFFC0FF
> PARAMETER C_WRITE_FSL_PORTS = 1
> BUS_INTERFACE MFSL0 = download_link
> BUS_INTERFACE SOPB = d_opb_v20
> PORT OPB_Clk = sys_clk
>END
>
>BEGIN fsl_v20
> PARAMETER INSTANCE = download_link
> PARAMETER HW_VER = 1.00.b
> PARAMETER C_EXT_RESET_HIGH = 0
> PORT SYS_Rst = sys_rst
> PORT FSL_Clk = sys_clk
>END
>
>BEGIN opb_sdram
> PARAMETER INSTANCE = SDRAM_4Mx16
> PARAMETER HW_VER = 1.00.d
> PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 0
> PARAMETER C_SDRAM_CAS_LAT = 2
> PARAMETER C_SDRAM_TRAS = 44000
> PARAMETER C_SDRAM_TRC = 66000
> PARAMETER C_SDRAM_TRCD = 20000
> PARAMETER C_SDRAM_TREF = 64
> PARAMETER C_SDRAM_TRFC = 66000
> PARAMETER C_SDRAM_TRP = 20000
> PARAMETER C_SDRAM_TRRD = 15000
> PARAMETER C_SDRAM_TCCD = 1
> PARAMETER C_SDRAM_COL_AWIDTH = 8
> PARAMETER C_SDRAM_BANK_AWIDTH = 2
> PARAMETER C_SDRAM_AWIDTH = 12
> PARAMETER C_SDRAM_DWIDTH = 16
> PARAMETER C_OPB_CLK_PERIOD_PS = 20000
> PARAMETER C_BASEADDR = 0x80000000
> PARAMETER C_HIGHADDR = 0x807fffff
> BUS_INTERFACE SOPB = d_opb_v20
> PORT OPB_Clk = sys_clk
> PORT SDRAM_CLK_in = sys_clk
> PORT SDRAM_WEn = SDRAM_4Mx16_SDRAM_WEn
> PORT SDRAM_CKE = SDRAM_4Mx16_SDRAM_CKE
> PORT SDRAM_CSn = SDRAM_4Mx16_SDRAM_CSn
> PORT SDRAM_CASn = SDRAM_4Mx16_SDRAM_CASn
> PORT SDRAM_RASn = SDRAM_4Mx16_SDRAM_RASn
> PORT SDRAM_Clk = SDRAM_4Mx16_SDRAM_Clk
> PORT SDRAM_Addr = SDRAM_4Mx16_SDRAM_Addr
> PORT SDRAM_BankAddr = SDRAM_4Mx16_SDRAM_BankAddr
> PORT SDRAM_DQ = SDRAM_4Mx16_SDRAM_DQ
>END
>
># BEGIN opb_emc
># PARAMETER INSTANCE = sram_flash
># PARAMETER HW_VER   = 1.10.b
># PARAMETER C_OPB_CLK_PERIOD_PS = 15000
># PARAMETER C_NUM_BANKS_MEM                = 2
># PARAMETER C_MAX_MEM_WIDTH                = 32
># PARAMETER C_MEM0_WIDTH                   = 32
># PARAMETER C_MEM1_WIDTH                   = 32
># PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
># PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_1 = 0
># PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_0      = 150000
># PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_0     = 55000
># PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_0      = 70000
># PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_0      = 150000
># PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_0     = 55000
># PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_0 = 15000
># PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_0 = 35000
># PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_1      = 150000
># PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_1     = 55000
># PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_1      = 70000
># PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_1      = 150000
># PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_1     = 55000
># PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_1 = 15000
># PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_1 = 35000
># PARAMETER C_BASEADDR      = 0xFFFF0000
># PARAMETER C_HIGHADDR      = 0xFFFF01FF
># PARAMETER C_MEM0_BASEADDR = 0xFFE00000
># PARAMETER C_MEM0_HIGHADDR = 0xFFEFFFFF
># PARAMETER C_MEM1_BASEADDR = 0xFF000000
># PARAMETER C_MEM1_HIGHADDR = 0xFF7FFFFF
># BUS_INTERFACE SOPB = d_opb_v20
># PORT OPB_Clk = sys_clk
># PORT Mem_CEN = sram_cen
># PORT Mem_A   = sram_addr_full
># PORT Mem_BEN = sram_ben
># PORT Mem_DQ  = sram_data
># PORT Mem_OEN = sram_oen_full
># PORT Mem_WEN = sram_wen
># PORT Mem_RPN = sram_rpn
># END
># BEGIN util_reduced_logic
># PARAMETER INSTANCE = oe_adj
># PARAMETER HW_VER   = 1.00.a
># PARAMETER C_SIZE      = 2
># PARAMETER C_OPERATION =  and
># PORT Op1 = sram_oen_full
># PORT Res = sram_oen
># END
># BEGIN util_bus_split
># PARAMETER INSTANCE = addr_adj
># PARAMETER HW_VER   = 1.00.a
># PARAMETER C_SIZE_IN  = 32
># PARAMETER C_LEFT_POS = 10
># PARAMETER C_SPLIT    = 30
># PORT Sig  = sram_addr_full
># PORT Out1 = sram_addr
># END
>
>BEGIN opb_uartlite
> PARAMETER INSTANCE = console_uart
> PARAMETER HW_VER = 1.00.b
> PARAMETER C_BAUDRATE = 57600
> PARAMETER C_DATA_BITS = 8
> PARAMETER C_USE_PARITY = 0
> PARAMETER C_ODD_PARITY = 0
> PARAMETER C_CLK_FREQ = 50000000
> PARAMETER C_BASEADDR = 0xFFFF2000
> PARAMETER C_HIGHADDR = 0xFFFF20FF
> BUS_INTERFACE SOPB = d_opb_v20
> PORT Interrupt = console_uart_interrupt
> PORT OPB_Clk = sys_clk
> PORT RX = console_uart_rx
> PORT TX = console_uart_tx
>END
>
>BEGIN opb_uartlite
> PARAMETER INSTANCE = debug_uart
> PARAMETER HW_VER = 1.00.b
> PARAMETER C_DATA_BITS = 8
> PARAMETER C_CLK_FREQ = 50000000
> PARAMETER C_BAUDRATE = 115200
> PARAMETER C_USE_PARITY = 0
> PARAMETER C_ODD_PARITY = 0
> PARAMETER C_BASEADDR = 0xFFFF4000
> PARAMETER C_HIGHADDR = 0xFFFF40FF
> BUS_INTERFACE SOPB = d_opb_v20
> PORT Interrupt = debug_uart_interrupt
> PORT OPB_Clk = sys_clk
> PORT RX = debug_uart_rx
> PORT TX = debug_uart_tx
>END
>
>BEGIN opb_intc
> PARAMETER INSTANCE = system_intc
> PARAMETER HW_VER = 1.00.c
> PARAMETER C_BASEADDR = 0xffff3000
> PARAMETER C_HIGHADDR = 0xffff30ff
> BUS_INTERFACE SOPB = d_opb_v20
> PORT Irq = interrupt
> PORT OPB_Clk = sys_clk
> PORT Intr = Ethernet_MAC_IP2INTC_Irpt & debug_uart_interrupt &
>console_uart_interrupt & timer_interrupt
>END
>
>BEGIN opb_timer
> PARAMETER INSTANCE = system_timer
> PARAMETER HW_VER = 1.00.b
> PARAMETER C_BASEADDR = 0xffff1000
> PARAMETER C_HIGHADDR = 0xffff10ff
> BUS_INTERFACE SOPB = d_opb_v20
> PORT OPB_Clk = sys_clk
> PORT Interrupt = timer_interrupt
>END
>
>BEGIN opb_gpio
> PARAMETER INSTANCE = system_gpio
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_BASEADDR = 0xffff5000
> PARAMETER C_HIGHADDR = 0xffff50ff
> PARAMETER C_GPIO_WIDTH = 8
> BUS_INTERFACE SOPB = d_opb_v20
> PORT GPIO_IO = gpio
> PORT OPB_Clk = sys_clk
>END
>
>BEGIN opb_ethernet
> PARAMETER INSTANCE = ethernet
> PARAMETER HW_VER = 1.00.m
> PARAMETER C_DMA_INTR_COALESCE = 1
> PARAMETER C_OPB_CLK_PERIOD_PS = 15000
> PARAMETER C_BASEADDR = 0xC0000000
> PARAMETER C_HIGHADDR = 0xC0003FFF
> BUS_INTERFACE SOPB = d_opb_v20
> PORT OPB_Clk = sys_clk
> PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
> PORT PHY_tx_er = Ethernet_MAC_PHY_tx_er
> PORT PHY_tx_clk = Ethernet_MAC_PHY_tx_clk
> PORT PHY_rx_clk = Ethernet_MAC_PHY_rx_clk
> PORT PHY_crs = Ethernet_MAC_PHY_crs
> PORT PHY_dv = Ethernet_MAC_PHY_dv
> PORT PHY_col = Ethernet_MAC_PHY_col
> PORT PHY_rx_er = Ethernet_MAC_PHY_rx_er
> PORT PHY_tx_en = Ethernet_MAC_PHY_tx_en
> PORT PHY_Mii_clk = Ethernet_MAC_PHY_Mii_clk
> PORT PHY_rst_n = Ethernet_MAC_PHY_rst_n
> PORT PHY_Mii_data = Ethernet_MAC_PHY_Mii_data
> PORT PHY_rx_data = Ethernet_MAC_PHY_rx_data
> PORT PHY_tx_data = Ethernet_MAC_PHY_tx_data
>END
>
>BEGIN lmb_bram_if_cntlr
> PARAMETER INSTANCE = d_lmb_bram_if_cntlr
> PARAMETER HW_VER = 1.00.b
> PARAMETER C_BASEADDR = 0x00000000
> PARAMETER C_HIGHADDR = 0x00003FFF
> BUS_INTERFACE SLMB = d_lmb_v10
> BUS_INTERFACE BRAM_PORT = conn_0
>END
>
>BEGIN lmb_bram_if_cntlr
> PARAMETER INSTANCE = i_lmb_bram_if_cntlr
> PARAMETER HW_VER = 1.00.b
> PARAMETER C_BASEADDR = 0x00000000
> PARAMETER C_HIGHADDR = 0x00003FFF
> BUS_INTERFACE SLMB = i_lmb_v10
> BUS_INTERFACE BRAM_PORT = conn_1
>END
>
>BEGIN bram_block
> PARAMETER INSTANCE = bram
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_MEMSIZE = 16384
> BUS_INTERFACE PORTA = conn_0
> BUS_INTERFACE PORTB = conn_1
>END
>
>BEGIN opb_v20
> PARAMETER INSTANCE = d_opb_v20
> PARAMETER HW_VER = 1.10.b
> PARAMETER C_EXT_RESET_HIGH = 0
> PORT OPB_Clk = sys_clk
> PORT SYS_Rst = sys_rst
>END
>
>BEGIN lmb_v10
> PARAMETER INSTANCE = i_lmb_v10
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_EXT_RESET_HIGH = 0
> PORT LMB_Clk = sys_clk
> PORT SYS_Rst = sys_rst
>END
>
>BEGIN lmb_v10
> PARAMETER INSTANCE = d_lmb_v10
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_EXT_RESET_HIGH = 0
> PORT LMB_Clk = sys_clk
> PORT SYS_Rst = sys_rst
>END
>
>Thanks, 
>
>Rich
>
>
>-----Original Message-----
>From: owner-microblaze-uclinux@itee.uq.edu.au
>[mailto:owner-microblaze-uclinux@itee.uq.edu.au] On Behalf Of aurash
>Sent: Wednesday, October 06, 2004 1:23 AM
>To: microblaze-uclinux@itee.uq.edu.au
>Subject: Re: [microblaze-uclinux] Porting help
>
>Richard,
>
>Can you share the MHS file with us?
>maybe we can spot the problem, looks like hardware to me!
>
>btw: leave the HW multiplier alone it should work on sp3
>and another question how did you test the SDRAM ( I hope not my writing 
>00 and FF)
>
>Aurash
>
>Richard Klosinski wrote:
>
>  
>
>>And another thing....
>>
>>I modified the heartbeat routine to toggle the state of the led, instead of
>>setting it based upon the input "value" (which I have no clue why you would
>>not want the led's to flash). 
>>
>>My led's flash at about a one second rate. Im not sure how much of the
>>system has to be working to get the led's to flash, but its has a timer set
>>and an interrupt vector working!
>>
>>Rich
>>
>>-----Original Message-----
>>From: owner-microblaze-uclinux@itee.uq.edu.au
>>[mailto:owner-microblaze-uclinux@itee.uq.edu.au] On Behalf Of John Williams
>>Sent: Tuesday, October 05, 2004 9:17 PM
>>To: microblaze-uclinux@itee.uq.edu.au
>>Subject: Re: [microblaze-uclinux] Porting help
>>
>>Hi Richard,
>>
>>Richard Klosinski wrote:
>> 
>>
>>    
>>
>>>Well, I'm stepping through the code as I type...
>>>
>>>I have already:
>>>-removed the cache from the mbvanilla design.
>>>-set the clock correctly in the mhs and verified the ports work ok
>>>-ERAM was already reduced in the mbvanilla design.
>>>
>>>I can find were the multiplier is disabled in either linux or xilinx. Can
>>>you please point me in the right direction.
>>>   
>>>
>>>      
>>>
>>Same place as the caches/ divider/barrel shifter etc:
>>
>>uClinux-dist/ $ make menuconfig
>>
>>kernel/library/defaults selection  -->
>>Customise Kernel Settings
>>
>>(exit, exit, yes)
>>
>>Processor type and features -->
>>
>>[ ] Hardware multiplier  (deselect)
>>[ ] Hardware dividier  (deselect)
>>[ ] Hardware Barrel Shift  (deselect)
>>[ ] Instruction cache  (deselect)
>>...
>>[ ] Data Cache  (deselect)
>>
>>
>>(exit, exit, yes)
>>
>>$ make dep
>>$ make
>>
>>Cheers,
>>
>>John
>>___________________________
>>microblaze-uclinux mailing list
>>microblaze-uclinux@itee.uq.edu.au
>>Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
>>Mailing List Archive :
>>http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
>>
>>
>>___________________________
>>microblaze-uclinux mailing list
>>microblaze-uclinux@itee.uq.edu.au
>>Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
>>Mailing List Archive :
>>    
>>
>http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
>  
>
>> 
>>
>>    
>>
>
>
>___________________________
>microblaze-uclinux mailing list
>microblaze-uclinux@itee.uq.edu.au
>Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
>Mailing List Archive :
>http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
>
>
>
>___________________________
>microblaze-uclinux mailing list
>microblaze-uclinux@itee.uq.edu.au
>Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
>Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
>
>
>  
>


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