Re: [microblaze-uclinux] general questions S-IIE

["Rick HORMIGO \(L\)" <ricklist@xxxxxxxxxxx>]

Yes, having a external MAC+Phy could be even a nice win in resources in the FPGA. I know the phys are very compatible among
manufacturers specially if you use the MII interface, what about the MAC side? If one part goes obsolete worry me the trouble of
having new part working (i.e hardware + driver changes). Sounds like researching that MAC lite a bit more will be worth the
time.

By the way, Feb 05 are coming the first samples for 4VP FX12 (if you wanna believe Xilinx). With similar resources than a 2VP7 +
DSP hardware + 2 silicon MAC's - Rocket IO. Perfect match for embedded reconfigurable systems, although for that chip the
perfect fit is to use its PPC405 silicon.

Rickote.


----- Original Message -----
From: "John Williams" <jwilliams@itee.uq.edu.au>
To: <microblaze-uclinux@itee.uq.edu.au>
Sent: Wednesday, October 13, 2004 6:05 PM
Subject: Re: [microblaze-uclinux] general questions S-IIE


>
> Richard Klosinski wrote:
> > You need 8k of bram at 0 for vectors, etc, and another 8kx2 for cache.
> > You can run w/o cache, but at 10^th speed. Also, mac sucks up bram for
> > fifos’. Opencore.org has a free mac, but I don’t know if drivers are
> > available, and you will still need a phy chip. I might go external.
>
> Just to clarify, you could use a minimum-sized BRAM block (2K?) at
> address zero for the vectors - you just need some way to get the kernel
> image into external RAM and launch it.
>
> Also re: external MAC/PHY, I agree with your analysis - since you need a
> an external PHY chip anyway (AFAIK FPGA IO can't drive the magnetics
> directly), you might as well move the MAC out there as well and save the
> LUTs/BRAMS for something more interesting.
>
> Cheers,
>
> John
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