RE: [microblaze-uclinux] Odd Microblaze behavior

["Richard Klosinski" <rklosinski@xxxxxxxxxxxxx>]

Here is the code and small disassembly

	4	int a;
	5	
	6	   a = 33;
	0x2dc	<main+16>:		addik	r3, r0, 33	// 0x21
<_start1+9>
-	0x2e0	<main+20>:		swi	r3, r19, 28
	7	   a = 33;
-	0x2e4	<main+24>:		addik	r3, r0, 33	// 0x21
<_start1+9>
-	0x2e8	<main+28>:		swi	r3, r19, 28

As I step through main+16 and stop at main+20, r3 = 0x2fd, NOT 33. Stopping
at main+28, r3 = 0x21. The only registers that are changing are r3 and rpc.

This behavior happens all through my code, making it impossible to boot my
ucLinux from flash, as I cannot run code out of bram.  I relocated my flash
code to upper memory, and I was able to erase and program flash w/o a
problem.

When I make the elk project commenting out both caches, the code runs fine.
MHS snip:
BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_DIV = 1
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 4
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_CACHE_BYTE_SIZE = 4096
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_DCACHE_BYTE_SIZE = 4096
 PARAMETER C_ICACHE_BASEADDR = 0x80000000
 PARAMETER C_ICACHE_HIGHADDR = 0x807fffff
 PARAMETER C_ALLOW_ICACHE_WR = 1
 PARAMETER C_ADDR_TAG_BITS = 12
 PARAMETER C_DCACHE_BASEADDR = 0x80000000
 PARAMETER C_DCACHE_HIGHADDR = 0x807fffff
 PARAMETER C_DCACHE_ADDR_TAG = 12
 PARAMETER C_ALLOW_DCACHE_WR = 1
 PARAMETER C_FSL_LINKS = 1
 PARAMETER C_USE_MSR_INSTR = 1
 BUS_INTERFACE SFSL0 = download_link
 BUS_INTERFACE DLMB = d_lmb_v10
 BUS_INTERFACE ILMB = i_lmb_v10
 BUS_INTERFACE DOPB = d_opb_v20
 BUS_INTERFACE IOPB = d_opb_v20
 PORT CLK = sys_clk
 PORT INTERRUPT = interrupt
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = i_lmb_bram_if_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_MASK = 0x80000000
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001FFF
 BUS_INTERFACE SLMB = i_lmb_v10
 BUS_INTERFACE BRAM_PORT = conn_1
END

Note that the cache is only for the sdram, as the bram runs at opb speeds,
and does not need to be cached.






-----Original Message-----
From: owner-microblaze-uclinux@itee.uq.edu.au
[mailto:owner-microblaze-uclinux@itee.uq.edu.au] On Behalf Of John Williams
Sent: Wednesday, October 20, 2004 3:28 AM
To: microblaze-uclinux@itee.uq.edu.au
Subject: Re: [microblaze-uclinux] Odd Microblaze behavior

Hi Richard,

Richard Klosinski wrote:

> int main (void)
> {
> 	volatile int a;
> 
> 	a = 33;
> 	a = 33;
> }
> Background.
> Compiled with optimization off.
> Executing out of bram, not external memory (which it will work fine in).
> Cache is on (the code works if cache is off)

Which cache - data or instruction?

Just a heads-up - you should not allow the cacheable range to overlap 
the LMB memory range - it doesn't make sense, and result may be undefined..

> Problem.
> Stopping at the first 'a=33', the debugger indicates a = 765. I checked
its
> address, and yeap, 765. Stepping to the next 'a=33', a finally = 33. This
> behavior happens all through the code. 

Odd.  Can you post the output of

$ mb-objdump -S mycode.o

for this particular code fragment?  It will show exactly what assembly 
instructions were generated by the compiler.  But really this looks more 
like a cache induced gdb artifact or something like that.

Finally, is this uClinux application code?  Or stand alone (bare-metal)?

John
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