Re: [microblaze-uclinux] RE: uclinux port to Multimedia board

[aurash <aurelian.lazarut@xxxxxxxxxxx>]

Chis,

FOR SURE the cache size is not the root cause because are COMMENTED OUT 
(I didn't have the chance to drink my cofee)
but keep in mind to adjust the correct the size when you enable the cache

Aurash

Christopher John Comis wrote:

>Hi,
>
>The system.mhs is attached.
>
>Thanks,
>Chris
>
>
>  
>
>>-----Original Message-----
>>From: owner-microblaze-uclinux@itee.uq.edu.au [mailto:owner-microblaze-
>>uclinux@itee.uq.edu.au] On Behalf Of aurash
>>Sent: October 22, 2004 1:47 PM
>>To: microblaze-uclinux@itee.uq.edu.au
>>Subject: Re: [microblaze-uclinux] RE: uclinux port to Multimedia board
>>
>>Chris,
>>
>>Please post the MHS file so we ca take a look.
>>very likely is something to do with the interrupts or timer
>>Aurash
>>
>>Christopher John Comis wrote:
>>
>>    
>>
>>>Small correction:
>>>
>>>My first bank of memory ranges as follows:
>>>PARAMETER C_MEM0_BASEADDR = 0xFFE00000
>>>PARAMETER C_MEM0_HIGHADDR = 0xFFEFFFFF
>>>
>>>Chris
>>>
>>>
>>>
>>>
>>>      
>>>
>>>>-----Original Message-----
>>>>From: Christopher John Comis [mailto:comis@eecg.toronto.edu]
>>>>Sent: October 22, 2004 11:52 AM
>>>>To: 'microblaze-uclinux@itee.uq.edu.au'
>>>>Subject: uclinux port to Multimedia board
>>>>
>>>>
>>>>Hi,
>>>>
>>>>I am wondering if any of you could please help me out.  I am trying to
>>>>port to the Xilinx Multimedia board.  I made several modifications to
>>>>accommodate the mbvanilla platform to my board:
>>>>- I removed the DDR
>>>>- I removed cache from the microblaze (which used the DDR memory)
>>>>- I replaced the sram_flash emc with an emc for my ZBT RAM.  I then set
>>>>the base addresses as follows:
>>>>- I set 1MB of my ZBT RAM to base address 0xFE000000-0xFEFFFFFF
>>>>- I set 8MB of my ZBT RAM to base address 0xFF000000-0xFF7FFFFF (note
>>>>        
>>>>
>>that
>>    
>>
>>>>this memory is actually divided across 4x2MB banks)
>>>>- I modified the DCM clocking mechanism (first DCM is for the opb,
>>>>        
>>>>
>>second
>>    
>>
>>>>DCM is for the onboard ZBT memory)
>>>>
>>>>I can download the platform, launch mdm and ran a memory test that
>>>>verifies the memory is instantiated correctly.
>>>>
>>>>I made the following modifications to the uclinux platform:
>>>>- I adjusted mbvanilla.h as follows:
>>>>#define ERAM_ADDR 0xFFE00000
>>>>#define ERAM_SIZE 0x00100000
>>>>- I adjusted the address space of mbvanilla.ld as follows:
>>>>OPB  : ORIGIN = 0xFFE00000, LENGTH = 0x00100000
>>>>- I verified that the following options were set in config.linux-2.4.x
>>>># CONFIG_MICROBLAZE_ICACHE is not set
>>>># CONFIG_MICROBLAZE_DCACHE is not set
>>>>
>>>>When I launch mdm, download and run image.elf, things are smooth until
>>>>        
>>>>
>>the
>>    
>>
>>>>line:
>>>>Calibrating delay loop...
>>>>At which point the program freezes.
>>>>
>>>>Reading previous posts, my intc interrupt port is set as follows:
>>>>PORT Intr = Ethernet_MAC_IP2INTC_Irpt & debug_uart_interrupt &
>>>>console_uart_interrupt & timer_interrupt
>>>>(note that my dummy debug uart is connected to a LED for output and a
>>>>switch for input)
>>>>I also modified the config.linux-2.4.x under both cases:
>>>>CONFIG_MICROBLAZE_HARD_MULT=y
>>>>CONFIG_MICROBLAZE_HARD_MULT=n
>>>>
>>>>Am I missing something?  Can someone (anyone??) please help me out?
>>>>Thanks
>>>>Chris
>>>>
>>>>
>>>>        
>>>>
>>>___________________________
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>>>      
>>>
>>uclinux/
>>    
>>
>>>
>>>
>>>      
>>>
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>>uclinux/
>>    
>>
>
>  
>


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