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Re: [microblaze-uclinux] uclinux port to Multimedia board
Hi,
John Williams wrote:
> Hi Didier,
>
> Can you post your MHS file? There's something fundamental missing here
> - you shouldn't be having all this trouble!
>
> Thanks,
>
> John
my mhs file is attached. I'm using EDK 6.1 and it's based on the
mbvanilla_net_v6.1d
The interrupt controller has been tested with a little test programm and
it's working.
Thanks for your help.
Regards,
Didier
# Parameters
PARAMETER VERSION = 2.1.0
# Global Ports
PORT sys_clk = sys_clk, DIR = IN
#PORT ddr_clk_fb = ddr_clk_fb, DIR = IN
PORT EXTEND_DCM_RESET_P = EXTEND_DCM_RESET_P, DIR = IN
PORT ENET_SLEW_P = ENET_SLEW_P, VEC = [1:0], DIR = OUT
#PORT MDC_P = MDC_P, DIR = OUT
#PORT MDIO_P = MDIO_P, DIR = OUT
PORT STARTUP_P = STARTUP_P, DIR = OUT
PORT reset_sys = sys_rstn, DIR = IN
PORT console_uart_rx = console_uart_rx, DIR = IN
PORT console_uart_tx = console_uart_tx, DIR = OUT
PORT debug_uart_rx = debug_uart_rx, DIR = IN
PORT debug_uart_tx = debug_uart_tx, DIR = OUT
PORT RS232_RTS_IN_P = net_gnd, DIR = OUT
#SRAM enlevée
#PORT sram_cen = sram_cen, DIR = OUT, VEC = [0:1]
#PORT sram_addr = sram_addr, DIR = OUT, VEC = [0:31]
#PORT sram_ben = sram_ben, DIR = OUT, VEC = [0:3]
#PORT sram_data = sram_data, DIR = INOUT, VEC = [0:31]
#PORT sram_oen = sram_oen, DIR = OUT
#PORT sram_wen = sram_wen, DIR = OUT
#PORT sram_rst = sram_rst, DIR = OUT
PORT gpio = gpio, DIR = INOUT, VEC = [0:23]
#DDR enlevée
#PORT ddr_clk = ddr_clk, DIR = OUT
#PORT ddr_clkn = ddr_clkn, DIR = OUT
#PORT ddr_clke = ddr_clke, DIR = OUT
#PORT ddr_csn = ddr_csn, DIR = OUT
#PORT ddr_rasn = ddr_rasn, DIR = OUT
#PORT ddr_casn = ddr_casn, DIR = OUT
#PORT ddr_wen = ddr_wen, DIR = OUT
#PORT ddr_dqm = ddr_dqm, DIR = OUT, VEC = [0:1]
#PORT ddr_bankaddr = ddr_bankaddr, DIR = OUT, VEC = [0:1]
#PORT ddr_addr = ddr_addr, DIR = OUT, VEC = [0:12]
#PORT ddr_dq = ddr_dq, DIR = INOUT, VEC = [0:15]
#PORT ddr_dqs = ddr_dqs, DIR = INOUT, VEC = [0:1]
#ethernet enlevé
PORT COLLISION_DETECTED_P = ETH_COL, DIR = IN
PORT CARRIER_SENSE_P = ETH_CRS, DIR = IN
PORT mdc_p = ETH_MDC, DIR = INOUT
PORT mdio_p = ETH_MDIO, DIR = INOUT
PORT RX_CLOCK_P = ETH_RXC, DIR = IN
PORT RX_DATA_P = ETH_RXD, DIR = IN, VEC = [3:0]
PORT RX_DATA_VALID_P = ETH_RXDV, DIR = IN
PORT RX_ERROR_P = ETH_RXER, DIR = IN
PORT TX_CLOCK_P = ETH_TXC, DIR = IN
PORT TX_DATA_P = ETH_TXD, DIR = OUT, VEC = [3:0]
PORT TX_ENABLE_P = ETH_TXEN, DIR = OUT
PORT TX_ERROR_P = ETH_TXER, DIR = OUT
PORT PHY_RESETn = PHY_RESETn, DIR = OUT
#ZBT
PORT MEMORY_BANK0_CLK_P = MEMORY_BANK2_CLK_P, DIR = OUT
PORT MEMORY_BANK1_CLK_P = MEMORY_BANK2_CLK_P, DIR = OUT
PORT MEMORY_BANK2_CLK_P = MEMORY_BANK2_CLK_P, DIR = OUT
PORT MEMORY_BANK3_CLK_P = MEMORY_BANK2_CLK_P, DIR = OUT
PORT MEMORY_BANK4_CLK_P = MEMORY_BANK2_CLK_P, DIR = OUT
#0
PORT MEMORY_BANK0_ADDR_P = memory_bank0_addr_p, VEC = [0:18], DIR = OUT
PORT MEMORY_BANK0_ADV_LD_N = memory_bank0_adv_ld_n, DIR = OUT
PORT MEMORY_BANK0_WEN = memory_bank0_wen, VEC = [1:4], DIR = OUT
PORT MEMORY_BANK0_CEN_N = memory_bank0_cen_n, DIR = OUT
PORT MEMORY_BANK0_CLKEN_N = memory_bank0_clken_n, DIR = OUT
PORT MEMORY_BANK0_DATA = memory_bank0_data, VEC = [0:31], DIR = INOUT
PORT MEMORY_BANK0_OEN_N = memory_bank0_oen_n, DIR = OUT
PORT MEMORY_BANK0_WEN_N = memory_bank0_wen_n, DIR = OUT
#1
PORT MEMORY_BANK1_ADDR_P = memory_bank1_addr_p, VEC = [0:18], DIR = OUT
PORT MEMORY_BANK1_ADV_LD_N = memory_bank1_adv_ld_n, DIR = OUT
PORT MEMORY_BANK1_WEN = memory_bank1_wen, VEC = [1:4], DIR = OUT
PORT MEMORY_BANK1_CEN_N = memory_bank1_cen_n, DIR = OUT
PORT MEMORY_BANK1_CLKEN_N = memory_bank1_clken_n, DIR = OUT
PORT MEMORY_BANK1_DATA = memory_bank1_data, VEC = [0:31], DIR = INOUT
PORT MEMORY_BANK1_OEN_N = memory_bank1_oen_n, DIR = OUT
PORT MEMORY_BANK1_WEN_N = memory_bank1_wen_n, DIR = OUT
#2
PORT MEMORY_BANK2_ADDR_P = memory_bank2_addr_p, VEC = [0:18], DIR = OUT
PORT MEMORY_BANK2_ADV_LD_N = memory_bank2_adv_ld_n, DIR = OUT
PORT MEMORY_BANK2_WEN = memory_bank2_wen, VEC = [1:4], DIR = OUT
PORT MEMORY_BANK2_CEN_N = memory_bank2_cen_n, DIR = OUT
PORT MEMORY_BANK2_CLKEN_N = memory_bank2_clken_n, DIR = OUT
PORT MEMORY_BANK2_DATA = memory_bank2_data, VEC = [0:31], DIR = INOUT
PORT MEMORY_BANK2_OEN_N = memory_bank2_oen_n, DIR = OUT
PORT MEMORY_BANK2_WEN_N = memory_bank2_wen_n, DIR = OUT
#3
PORT MEMORY_BANK3_ADDR_P = memory_bank3_addr_p, VEC = [0:18], DIR = OUT
PORT MEMORY_BANK3_ADV_LD_N = memory_bank3_adv_ld_n, DIR = OUT
PORT MEMORY_BANK3_WEN = memory_bank3_wen, VEC = [1:4], DIR = OUT
PORT MEMORY_BANK3_CEN_N = memory_bank3_cen_n, DIR = OUT
PORT MEMORY_BANK3_CLKEN_N = memory_bank3_clken_n, DIR = OUT
PORT MEMORY_BANK3_DATA = memory_bank3_data, VEC = [0:31], DIR = INOUT
PORT MEMORY_BANK3_OEN_N = memory_bank3_oen_n, DIR = OUT
PORT MEMORY_BANK3_WEN_N = memory_bank3_wen_n, DIR = OUT
#4
PORT MEMORY_BANK4_ADDR_P = memory_bank4_addr_p, VEC = [0:18], DIR = OUT
PORT MEMORY_BANK4_ADV_LD_N = memory_bank4_adv_ld_n, DIR = OUT
PORT MEMORY_BANK4_WEN = memory_bank4_wen, VEC = [1:4], DIR = OUT
PORT MEMORY_BANK4_CEN_N = memory_bank4_cen_n, DIR = OUT
PORT MEMORY_BANK4_CLKEN_N = memory_bank4_clken_n, DIR = OUT
PORT MEMORY_BANK4_DATA = memory_bank4_data, VEC = [0:31], DIR = INOUT
PORT MEMORY_BANK4_OEN_N = memory_bank4_oen_n, DIR = OUT
PORT MEMORY_BANK4_WEN_N = memory_bank4_wen_n, DIR = OUT
# Sub Components
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_USE_DIV = 1
PARAMETER C_USE_BARREL = 1
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 2
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 2
#cache enlevé
#PARAMETER C_USE_ICACHE = 1
#PARAMETER C_ICACHE_BASEADDR = 0x80000000
#PARAMETER C_ICACHE_HIGHADDR = 0x81FFFFFF
#PARAMETER C_CACHE_BYTE_SIZE = 16384
#PARAMETER C_ADDR_TAG_BITS = 11
#PARAMETER C_USE_DCACHE = 1
#PARAMETER C_DCACHE_BASEADDR = 0x80000000
#PARAMETER C_DCACHE_HIGHADDR = 0x81FFFFFF
#PARAMETER C_DCACHE_BYTE_SIZE = 16384
#PARAMETER C_DCACHE_ADDR_TAG = 11
BUS_INTERFACE DLMB = d_lmb_v10
BUS_INTERFACE ILMB = i_lmb_v10
BUS_INTERFACE DOPB = d_opb_v20
BUS_INTERFACE IOPB = d_opb_v20
PORT CLK = sys_clk
PORT INTERRUPT = interrupt
END
# inverter to convert active low sys_rstn to active high sys_rst
BEGIN my_inverter
PARAMETER INSTANCE = rst_inverter
PORT I = sys_rstn
PORT O = sys_rst
END
#DDR enlevé
#BEGIN ddr_clk_gen
# PARAMETER INSTANCE = my_ddr_clk_gen
# PARAMETER HW_VER = 1.00.a
## 66mhz internal clock
# PARAMETER C_CLKIN_PERIOD_NS = 15.0
## 66mhz external clock
# PORT CLK_IN = clk66mhz
## tie DCM reset to system reset (active low)
# PORT CLK_RST = sys_rst
## feedback from outside
# PORT DDR_CLK_FB = ddr_clk_fb
## drive system clock with this one
# PORT CLK0 = sys_clk
## 90 deg phase shifted system clock
# PORT CLK90 = sys_clk_90
## external feedback 90 deg phase shift
# PORT DDR_CLK_90 = ddr_clk_90
#END
## PORT CORE_DCM_LOCKED = core_dcm_locked
## PORT DDR_DCM_LOCKED = ddr_dcm_locked
#BEGIN opb_ddr
# PARAMETER INSTANCE = ddr_controller
# PARAMETER HW_VER = 1.00.b
## 100mhz clock
# PARAMETER C_OPB_CLK_PERIOD_PS = 15000
# PARAMETER C_INCLUDE_BURST_SUPPORT = 0
# PARAMETER C_DQS_PULLUPS = 1
# PARAMETER C_REG_DIMM = 0
# PARAMETER C_DDR_TMRD = 15000
# PARAMETER C_DDR_TWR = 15000
# PARAMETER C_DDR_TWTR = 1
# PARAMETER C_DDR_TRAS = 40000
# PARAMETER C_DDR_TRC = 65000
# PARAMETER C_DDR_TRFC = 75000
# PARAMETER C_DDR_TRCD = 20000
# PARAMETER C_DDR_TRRD = 15000
# PARAMETER C_DDR_TREFC = 70000000
# PARAMETER C_DDR_TREFI = 7800000
# PARAMETER C_DDR_TRP = 20000
# PARAMETER C_DDR_CAS_LAT = 2
# PARAMETER C_DDR_DWIDTH = 16
# PARAMETER C_DDR_AWIDTH = 13
# PARAMETER C_DDR_COL_AWIDTH = 9
# PARAMETER C_DDR_BANK_AWIDTH = 2
# PARAMETER C_BASEADDR = 0x80000000
# PARAMETER C_HIGHADDR = 0x81FFFFFF
# BUS_INTERFACE SOPB = d_opb_v20
## system clock
# PORT OPB_Clk = sys_clk
## phase shifted sys_clk
# PORT Clk90_in = sys_clk_90
## phase shifted feedback clk
# PORT DDR_Clk90_in = ddr_clk_90
## output clocks
# PORT DDR_Clk = ddr_clk
## inverted clock
# PORT DDR_Clkn = ddr_clkn
# PORT DDR_CKE = ddr_clke
# PORT DDR_CSn = ddr_csn
# PORT DDR_RASn = ddr_rasn
# PORT DDR_CASn = ddr_casn
# PORT DDR_WEn = ddr_wen
# PORT DDR_DM = ddr_dqm
# PORT DDR_BankAddr = ddr_bankaddr
# PORT DDR_Addr = ddr_addr
# PORT DDR_DQ = ddr_dq
# PORT DDR_DQS = ddr_dqs
#END
#on utilise opb_zbt_controller à la place
#BEGIN opb_memcon
# PARAMETER INSTANCE = system_memcon
# PARAMETER HW_VER = 1.00.a
# PARAMETER C_OPB_CLOCK_PERIOD_PS = 15000
# PARAMETER C_NUM_BANKS_MEM = 2
# PARAMETER C_BASEADDR = 0xffff0000
# PARAMETER C_HIGHADDR = 0xffff00ff
# PARAMETER C_MEM0_BASEADDR = 0xffe00000
# PARAMETER C_MEM0_HIGHADDR = 0xffefffff
# PARAMETER C_MEM1_BASEADDR = 0xff000000
# PARAMETER C_MEM1_HIGHADDR = 0xff7fffff
# BUS_INTERFACE SOPB = d_opb_v20
# PORT Mem_CEN = sram_cen
# PORT Mem_A = sram_addr
# PORT Mem_BEN = sram_ben
# PORT Mem_DQ = sram_data
# PORT Mem_OEN = sram_oen
# PORT Mem_WEN = sram_wen
# PORT OPB_Clk = sys_clk
# PORT Mem_RPN = sram_rst
#END
BEGIN opb_uartlite
PARAMETER INSTANCE = console_uart
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 57600
PARAMETER C_DATA_BITS = 8
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 0
#on utilise la bonne fréquence
#PARAMETER C_CLK_FREQ = 66_666_667
PARAMETER C_CLK_FREQ = 27_000_000
PARAMETER C_BASEADDR = 0xFFFF2000
PARAMETER C_HIGHADDR = 0xFFFF20FF
BUS_INTERFACE SOPB = d_opb_v20
PORT Interrupt = console_uart_interrupt
PORT OPB_Clk = sys_clk
PORT RX = console_uart_rx
PORT TX = console_uart_tx
END
BEGIN opb_uartlite
PARAMETER INSTANCE = debug_uart
PARAMETER HW_VER = 1.00.b
PARAMETER C_DATA_BITS = 8
#on utilise la bonne fréquence
#PARAMETER C_CLK_FREQ = 66_666_667
PARAMETER C_CLK_FREQ = 27_000_000
PARAMETER C_BAUDRATE = 115200
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 0
PARAMETER C_BASEADDR = 0xFFFF4000
PARAMETER C_HIGHADDR = 0xFFFF40FF
BUS_INTERFACE SOPB = d_opb_v20
PORT Interrupt = debug_uart_interrupt
PORT OPB_Clk = sys_clk
PORT RX = debug_uart_rx
PORT TX = debug_uart_tx
END
BEGIN opb_intc
PARAMETER INSTANCE = system_intc
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0xffff3000
PARAMETER C_HIGHADDR = 0xffff30ff
PARAMETER C_KIND_OF_INTR = B 0111
PARAMETER C_KIND_OF_EDGE = B X111
PARAMETER C_KIND_OF_LVL = B 1XXX
BUS_INTERFACE SOPB = d_opb_v20
PORT Irq = interrupt
PORT OPB_Clk = sys_clk
#ethernet enlevé
PORT Intr = ethernet_interrupt & debug_uart_interrupt & console_uart_interrupt & timer_interrupt
#PORT Intr = ethernet_interrupt & debug_uart_interrupt & timer_interrupt & console_uart_interrupt
#PORT Intr = debug_uart_interrupt & console_uart_interrupt & timer_interrupt
END
BEGIN opb_timer
PARAMETER INSTANCE = system_timer
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0xffff1000
PARAMETER C_HIGHADDR = 0xffff10ff
BUS_INTERFACE SOPB = d_opb_v20
PORT OPB_Clk = sys_clk
PORT Interrupt = timer_interrupt
END
BEGIN opb_gpio
PARAMETER INSTANCE = system_gpio
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0xffff5000
PARAMETER C_HIGHADDR = 0xffff50ff
PARAMETER C_GPIO_WIDTH = 24
BUS_INTERFACE SOPB = d_opb_v20
PORT GPIO_IO = gpio
PORT OPB_Clk = sys_clk
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = d_lmb_bram_if_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003FFF
BUS_INTERFACE SLMB = d_lmb_v10
BUS_INTERFACE BRAM_PORT = conn_0
PORT LMB_Clk = sys_clk
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = i_lmb_bram_if_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003FFF
BUS_INTERFACE SLMB = i_lmb_v10
BUS_INTERFACE BRAM_PORT = conn_1
PORT LMB_Clk = sys_clk
END
BEGIN bram_block
PARAMETER INSTANCE = bram
PARAMETER HW_VER = 1.00.a
PARAMETER C_MEMSIZE = 16384
BUS_INTERFACE PORTA = conn_0
BUS_INTERFACE PORTB = conn_1
END
BEGIN opb_v20
PARAMETER INSTANCE = d_opb_v20
PARAMETER HW_VER = 1.10.b
PORT OPB_Clk = sys_clk
PORT SYS_Rst = sys_rst
END
BEGIN lmb_v10
PARAMETER INSTANCE = i_lmb_v10
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk
PORT SYS_Rst = sys_rst
END
BEGIN lmb_v10
PARAMETER INSTANCE = d_lmb_v10
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk
PORT SYS_Rst = sys_rst
END
#BEGIN my_dcm
# PARAMETER INSTANCE = system_dcm
# PARAMETER HW_VER = 1.00.a
# PARAMETER C_CLKIN_PERIOD_NS = 10.0
# PARAMETER C_DIVISOR = 3
# PARAMETER C_INBUFFER = TRUE
# PARAMETER C_MULTIPLIER = 2
# PARAMETER C_OUTBUFFER = TRUE
## external clock input pin
# PORT CLK_IN = ext_clk
# PORT CLK_RST = net_gnd
# PORT CLK_0 = clk_fb_o
# PORT CLK_FB = clk_fb_i
## input to ddr_clk_gen module
# PORT CLK_FX = clk66mhz
#END
BEGIN my_bufg
PARAMETER INSTANCE = dcm_feedback_bufg
PORT I = clk_fb_o
PORT O = clk_fb_i
END
BEGIN opb_mdm
PARAMETER INSTANCE = mdm
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0xffff7000
PARAMETER C_HIGHADDR = 0xffff70ff
BUS_INTERFACE SOPB = d_opb_v20
PORT OPB_Clk = sys_clk
END
#ethernet enlevé
BEGIN opb_ethernet
PARAMETER INSTANCE = ether
PARAMETER HW_VER = 1.00.m
PARAMETER C_DMA_PRESENT = 1
PARAMETER C_DMA_INTR_COALESCE = 1
#Modification de la pérode OPB
#PARAMETER C_OPB_CLK_PERIOD_PS = 15000
PARAMETER C_OPB_CLK_PERIOD_PS = 12_345
PARAMETER C_BASEADDR = 0xC0000000
PARAMETER C_HIGHADDR = 0xC0003FFF
BUS_INTERFACE MSOPB = d_opb_v20
PORT OPB_Clk = sys_clk
PORT OPB_Rst = sys_rst
PORT PHY_col = ETH_COL
PORT PHY_crs = ETH_CRS
PORT PHY_Mii_clk = ETH_MDC
PORT PHY_Mii_data = ETH_MDIO
PORT PHY_rx_clk = ETH_RXC
PORT PHY_rx_data = ETH_RXD
PORT PHY_dv = ETH_RXDV
PORT PHY_rx_er = ETH_RXER
PORT PHY_tx_clk = ETH_TXC
PORT PHY_tx_data = ETH_TXD
PORT PHY_tx_en = ETH_TXEN
PORT PHY_tx_er = ETH_TXER
PORT PHY_rst_n = PHY_RESETn
PORT Freeze = net_gnd
PORT IP2INTC_Irpt = ethernet_interrupt
END
BEGIN MicroBlaze_Brd_ZBT_ClkGen
PARAMETER INSTANCE = MicroBlaze_Brd_ZBT_ClkGen_0
PARAMETER HW_VER = 1.00.a
PORT clk_27mhz = clk_27mhz
PORT clk_81mhz = clk_81mhz
PORT ENET_SLEW_P = ENET_SLEW_P
PORT EXTEND_DCM_RESET_P = EXTEND_DCM_RESET_P
PORT fpga_reset = fpga_reset
PORT MASTER_CLOCK_P = sys_clk
PORT MDC_P = MDC_P
PORT MDIO_P = MDIO_P
PORT MEMORY_BANK2_CLK_P = MEMORY_BANK2_CLK_P
PORT MEM_CLK_FBOUT_P = MEM_CLK_FBOUT_P
PORT PAUSE_P = PAUSE_P
PORT STARTUP_P = STARTUP_P
END
BEGIN opb_zbt_controller
PARAMETER INSTANCE = opb_zbt_controller_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x80800000
PARAMETER C_HIGHADDR = 0x809FFFFF
PARAMETER C_ZBT_ADDR_SIZE = 19
PARAMETER C_EXTERNAL_DLL = 1
BUS_INTERFACE SOPB = d_opb_v20
PORT OPB_Clk = clk_81mhz
PORT ZBT_A = memory_bank0_addr_p
PORT ZBT_ADV_LD_N = memory_bank0_adv_ld_n
PORT ZBT_BW_N = memory_bank0_wen
PORT ZBT_CE1_N = memory_bank0_cen_n
PORT ZBT_CKE_N = memory_bank0_clken_n
PORT ZBT_IO = memory_bank0_data
PORT ZBT_OE_N = memory_bank0_oen_n
PORT ZBT_RW_N = memory_bank0_wen_n
END
BEGIN opb_zbt_controller
PARAMETER INSTANCE = opb_zbt_controller_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x80200000
PARAMETER C_HIGHADDR = 0x803FFFFF
PARAMETER C_ZBT_ADDR_SIZE = 19
PARAMETER C_EXTERNAL_DLL = 1
BUS_INTERFACE SOPB = d_opb_v20
PORT OPB_Clk = clk_81mhz
PORT ZBT_A = memory_bank1_addr_p
PORT ZBT_ADV_LD_N = memory_bank1_adv_ld_n
PORT ZBT_BW_N = memory_bank1_wen
PORT ZBT_CE1_N = memory_bank1_cen_n
PORT ZBT_CKE_N = memory_bank1_clken_n
PORT ZBT_IO = memory_bank1_data
PORT ZBT_OE_N = memory_bank1_oen_n
PORT ZBT_RW_N = memory_bank1_wen_n
END
BEGIN opb_zbt_controller
PARAMETER INSTANCE = opb_zbt_controller_2
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x80400000
PARAMETER C_HIGHADDR = 0x805FFFFF
PARAMETER C_ZBT_ADDR_SIZE = 19
PARAMETER C_EXTERNAL_DLL = 1
BUS_INTERFACE SOPB = d_opb_v20
PORT OPB_Clk = clk_81mhz
PORT ZBT_A = memory_bank2_addr_p
PORT ZBT_ADV_LD_N = memory_bank2_adv_ld_n
PORT ZBT_BW_N = memory_bank2_wen
PORT ZBT_CE1_N = memory_bank2_cen_n
PORT ZBT_CKE_N = memory_bank2_clken_n
PORT ZBT_IO = memory_bank2_data
PORT ZBT_OE_N = memory_bank2_oen_n
PORT ZBT_RW_N = memory_bank2_wen_n
END
BEGIN opb_zbt_controller
PARAMETER INSTANCE = opb_zbt_controller_3
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0xFF600000
PARAMETER C_HIGHADDR = 0xFF7FFFFF
PARAMETER C_ZBT_ADDR_SIZE = 19
PARAMETER C_EXTERNAL_DLL = 1
BUS_INTERFACE SOPB = d_opb_v20
PORT OPB_Clk = clk_81mhz
PORT ZBT_A = memory_bank3_addr_p
PORT ZBT_ADV_LD_N = memory_bank3_adv_ld_n
PORT ZBT_BW_N = memory_bank3_wen
PORT ZBT_CE1_N = memory_bank3_cen_n
PORT ZBT_CKE_N = memory_bank3_clken_n
PORT ZBT_IO = memory_bank3_data
PORT ZBT_OE_N = memory_bank3_oen_n
PORT ZBT_RW_N = memory_bank3_wen_n
END
BEGIN opb_zbt_controller
PARAMETER INSTANCE = opb_zbt_controller_4
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x80000000
PARAMETER C_HIGHADDR = 0x801FFFFF
PARAMETER C_ZBT_ADDR_SIZE = 19
PARAMETER C_EXTERNAL_DLL = 1
BUS_INTERFACE SOPB = d_opb_v20
PORT OPB_Clk = clk_81mhz
PORT ZBT_A = memory_bank4_addr_p
PORT ZBT_ADV_LD_N = memory_bank4_adv_ld_n
PORT ZBT_BW_N = memory_bank4_wen
PORT ZBT_CE1_N = memory_bank4_cen_n
PORT ZBT_CKE_N = memory_bank4_clken_n
PORT ZBT_IO = memory_bank4_data
PORT ZBT_OE_N = memory_bank4_oen_n
PORT ZBT_RW_N = memory_bank4_wen_n
END