That seemed to help, but I'm still not quite meeting timing:
--------------------------------------------------------------------------------
* PERIOD analysis for net "dcm_0/dcm_0/CLKF | 15.151ns | 16.932ns |
4
X_BUF" derived from NET "dcm_clk_s" PERI | | |
OD = 15.151 nS HIGH 50.000000 % | | |
I'm attaching my system.mhs and etc/fast_runtime.opt files.
Thanks for your help.
Steve
--- Göran Bilski <Goran.Bilski@xilinx.com> wrote:
> Try set this for MicroBlaze in the .mhs file
> PARAMETER C_NUMBER_OF_PC_BRK = 1
> PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 0
> PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 0
>
> It will remove the address watchpoints in the JTAG debug logic but
> normally that isn't used.
> The debug logic needs to stop the processor after the address has
> been
> generated and sometimes this gets in the critical path.
>
> Could you also send the etc/fast_runtime.opt file?
>
> Göran Bilski
>
>
> Steve Sanders wrote:
>
> >I've made some performance improvements to the Microblaze design I
> have
> >running on an 'S400 device. Helped quite a bit - boot log is
> telling
> >me 24.something BogoMIPS now instead of 1.something:
> >
> >Linux version 2.4.27-uc1 (ssanders@debian-rbr) (gcc version 2.95.3-4
> >Xil5
> >On node 0 totalpages: 256
> >zone(0): 256 pages.
> >zone(1): 0 pages.
> >zone(2): 0 pages.
> >CPU: MICROBLAZE
> >Console: xmbserial on UARTLite
> >Kernel command line:
> >Calibrating delay loop... 24.32 BogoMIPS
> >Memory: 1MB = 1MB total
> >Memory: 340KB available (458K code, 203K data, 28K init)
> >Dentry cache hash table entries: 512 (order: 0, 4096 bytes)
> >Inode cache hash table entries: 512 (order: 0, 4096 bytes)
> >Mount cache hash table entries: 512 (order: 0, 4096 bytes)
> >Buffer cache hash table entries: 1024 (order: 0, 4096 bytes)
> >Page-cache hash table entries: 1024 (order: 0, 4096 bytes)
> >POSIX conformance testing by UNIFIX
> >Linux NET4.0 for Linux 2.4
> >Based upon Swansea University Computer Society NET3.039
> >Microblaze UARTlite serial driver version 1.00
> >ttyS0 at 0xffff2000 (irq = 1) is a Microblaze UARTlite
> >Starting kswapd
> >Blkmem copyright 1998,1999 D. Jeff Dionne
> >Blkmem copyright 1998 Kenneth Albanowski
> >Blkmem 1 disk images:
> >0: 800A1F44-800A5743 [VIRTUAL 800A1F44-800A5743] (RO)
> >VFS: Mounted root (romfs filesystem) readonly.
> >Freeing init memory: 28K
> >/ $ munmap of non-mmaped memory by process 1 (msh): 16000000
> >
> >/ $ cd /bin
> >/bin $
> >
> >
> >A few changes made to the design to get this:
> >- improved SRAM (emc) timing parameters
> >- changed DCM parameters to get a 49.5MHz clock instead of a 33MHz
> >clock
> >- converted 16KB of block RAM from kernel-accessible to I/D cache
> >- enabled I and D cache in the kernel configuration
> >
> >One problem I'm having... I'd like to go to a 66MHz clock, but
> timing
> >breaks when I do - as reported in a Xilinx log file. (66MHz will
> >enable 100MHz Ethernet later on instead of just 10MHz...) Any
> >suggestions on how to get there? I'm coming from a primarily
> embedded
> >software background, and am not really an FPGA designer.
> >
> >I'm attaching my current system.mhs and .config files...
> >
> >Steve
> >
>
> ___________________________
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> microblaze-uclinux@itee.uq.edu.au
> Project Home Page :
> http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
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> http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
>
>
Attachment:
system.mhs
Description: system.mhs
Attachment:
fast_runtime.opt
Description: fast_runtime.opt