[microblaze-uclinux] Interfacing External SDRAM to Microblaze

[Robin Coxe <coxe@xxxxxxxxxxx>]

This is a response to a post from back in February:   I encountered 
similar readback errors with the Microblaze using EDK v 6.3 and the 
OPB_SDRAM controller version 1.00.e.  I'm using a custom-built board.   
Sometimes, the system would read back 16-bit words supposedly written to 
the column address directly above or below the one specified or it would 
just read back garbage.   I solved the problem by clocking the SDRAM 
directly with the OPB clock without feedback or an additional DCM.   I'm 
using a Micron 32Mx16 (48LC32M16A2-75) SDRAM and a 66 MHz OPB clock.    
I wrote a bunch of data to successive column addresses, then read it all 
back.  I calculated a 16-bit CRC during both the reads and writes and 
they match.   

Here's the MHS fragment:

BEGIN opb_sdram
 PARAMETER INSTANCE = opb_sdram_0
 PARAMETER HW_VER = 1.00.e
 PARAMETER C_FAMILY = virtex2
 PARAMETER C_INCLUDE_BURST_SUPPORT = 0
 PARAMETER C_SDRAM_TMRD = 2
 PARAMETER C_SDRAM_TWR = 22500
 PARAMETER C_SDRAM_TCCD = 1
 PARAMETER C_SDRAM_TRAS = 44000
 PARAMETER C_SDRAM_TRC = 66000
 PARAMETER C_SDRAM_TRFC = 66000
 PARAMETER C_SDRAM_TRCD = 20000
 PARAMETER C_SDRAM_TRRD = 15000
 PARAMETER C_SDRAM_TRP = 20000
 PARAMETER C_SDRAM_TREF = 64
 PARAMETER C_SDRAM_REFRESH_NUMROWS = 8192
 PARAMETER C_SDRAM_CAS_LAT = 2
 PARAMETER C_SDRAM_DWIDTH = 16
 PARAMETER C_SDRAM_AWIDTH = 13
 PARAMETER C_SDRAM_COL_AWIDTH = 10
 PARAMETER C_SDRAM_BANK_AWIDTH = 2
 PARAMETER C_SDRAM_TREFI = 7812500
 PARAMETER C_OPB_CLK_PERIOD_PS = 15000
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x7FFFFFFF
 BUS_INTERFACE SOPB = opb_v20_0
 PORT SDRAM_CKE = srcke
 PORT SDRAM_Clk = srclk
 PORT SDRAM_DQ = srdat
 PORT SDRAM_CSn = srcs_n
 PORT SDRAM_Clk_in = clk66
 PORT SDRAM_Addr = sradd
 PORT SDRAM_DQM = srdqm
 PORT SDRAM_RASn = srras_n
 PORT SDRAM_BankAddr = srba
 PORT OPB_Clk = clk66
 PORT SDRAM_CASn = srcas_n
 PORT SDRAM_WEn = srwe_n
END

Here is how I create the SDRAM address pointer in C:

                volatile ULONG *address;
                ULONG aoffset;

                aoffset= (nbank <<24) | (nrow << 11) | (ncol << 2);
                address    = (volatile ULONG *)(OPB_SDRAM_BASEADDR + 
aoffset);

Note that there are also big/little endian issues with the Micron 
SDRAM.  Pay close attention to Table 4 in the "OPB Synchronous DRAM 
(SDRAM) Controller Product Specification" (DS426).

Hope this helps...
Robin

*******************************************************************
Has anybody gotten the SDRAM on an Avnet Communications Memory Module to 
work with a Spartan 3-based Microblaze and uClinux? It has a beautiful 
64MB of SDRAM that will allow me to move beyond my current 1MB system. 
But I'm having trouble just reading/writing to memory via XMD.Values 
that I write out to any 1 32-bit word are getting read back from_every_ 
memory word read location. And then 16-bit writes only write out the 
lower 8 bits. And I read back the same value from 16-bit read even 
though I only did 1 write. Thanks for any suggestions on things to look 
at.... I've done a compare of the opb_sdram and Micron datasheets and am 
pretty sure I have the various opb_sdram parameters set up correctly.

Steve
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