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RE: [microblaze-uclinux] Kernel crash debug: No code generated for 'get_romfs_base()' function?

To: <microblaze-uclinux@xxxxxxxxxxxxxx>
Subject: RE: [microblaze-uclinux] Kernel crash debug: No code generated for 'get_romfs_base()' function?
From: "David Banas" <dbanas@xxxxxxxxxxxxxx>
Date: Thu, 17 Mar 2005 10:58:25 -0800
In-reply-to: <4238D4B0.2000905@snapgear.com>
Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxx
Thread-index: AcUqjf3+KjXFo4mbTYSQo6kZyFPN8wAi5VNw

John, Greg,

Thanks for helping me understand how all this works. Now that I've traced
through the assembly for that portion of the code, I see that the "intent"
of the original C code is, in fact, being carried out. As Claudio pointed
out previously, and as you've reiterated, it was the optimizations that were
making it hard to single-step through the code with GDB.

Attached is my filtered kernel ".config" file, as requested.

Do either of you have any ideas as to why my stack frame is loaded up with
seemingly infinitely recursive calls to "start_kernel" after a crash?

Thank you,

David Banas
Field Applications Engineer
Nu Horizons Electronics Corp.
2070 Ringwood Avenue
San Jose, CA 95131
(408)434-0800 - office
(415)846-5837 - cell
http://www.nuhorizons.com

-----Original Message-----
From: owner-microblaze-uclinux@itee.uq.edu.au
[mailto:owner-microblaze-uclinux@itee.uq.edu.au] On Behalf Of Greg Ungerer
Sent: Wednesday, March 16, 2005 4:52 PM
To: microblaze-uclinux@itee.uq.edu.au
Subject: Re: [microblaze-uclinux] Kernel crash debug: No code generated for
'get_romfs_base()' function?

Hi John, David,

John Williams wrote:
> David Banas wrote:
>> I was just single-stepping through the early boot sequence, under 
>> control of
>> gdb, and noticed that I couldn't stop on lines 153 or 154 of 'machine.c'.
>> Furthermore, those 2 lines didn't appear to be getting executed properly.
>> For instance, the 'get_romfs_base' function simply returns the starting
>> address of the '.BSS' segment. However, when I arrived at line 156, 
>> below, I
>> found 'src' to be equal to '0'! 'len' was also equal to '0'. And, so, no
>> copying of the '.romfs' section was being performed and, therefore, 
>> some of
>> my '.romfs' data was getting wiped out when the '.BSS' section was zeroed
>> out in the subsequent lines of code. (I can't imagine that having any 
>> of my
>> '.romfs' section erased is healthy.)
> 
> 
> BSS, being the stack segment, is not actually present in the raw kernel 

Normally the segment referred to as BSS only contains the un-initialized
data. Certainly true for the kernel, the stack is just setup somewhere
else in memory at runtime.

Regards
Greg




> image.  It's really just the promise of a memory section...  When 
> appending the romfs image to the kernel image to create image.bin, we 
> place the romfs immediately at the BSS address.  Then, in the early 
> setup we copy the romfs away from BSS to where it belongs, then zero the 
> BSS to get the initial kernel stack ready.
> 
> That said, it does seem a bit strange that your src and length values 
> for the romfs copy would be zero.  Can you please post your kernel 
> .config file (linux-2.4.x/.config)?  Preferably filtered to remove all 
> comment lines, otherwise it's a bit long.
> 
> 
>> I was very curious as to why these 2 lines were getting skipped. So, I 
>> used
>> gdb's 'info line' command to take a peek at them. I found (as you can 
>> see,
>> below) that there was no code being generated for them!!! 
>> (Incidentally, all
>> this analysis was performed immediately after freshly downloading both 
>> the
>> bit stream and the RAM image and before any instructions were allowed to
>> execute, just to ensure that I was not seeing the product of program
>> corruption due to errant code.)
> 
> 
> As Claudio says, compiler optimisations can make the code seem somewhat 
> strange in the debugging context, loops being re-ordered and so on. 
> However, simply reducing the -O level on the kernel is not easy - in 
> fact much of the kernel will not compile at -O0 due to vaious 
> optimisations wired into the coding style.  This is a generic Linux 
> thing, not just for Microblaze.  I think you'll find that in 
> arch/microblaze/Makefile you can probably specify -O1, at least that 
> will be a little less aggressive than -O2.
> 
> Regards,
> 
> John
> ___________________________
> microblaze-uclinux mailing list
> microblaze-uclinux@itee.uq.edu.au
> Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
> Mailing List Archive : 
> http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
> 
> 

-- 
------------------------------------------------------------------------
Greg Ungerer  --  Chief Software Dude       EMAIL:     gerg@snapgear.com
SnapGear -- a CyberGuard Company            PHONE:       +61 7 3435 2888
825 Stanley St,                             FAX:         +61 7 3891 3630
Woolloongabba, QLD, 4102, Australia         WEB: http://www.SnapGear.com
___________________________
microblaze-uclinux mailing list
microblaze-uclinux@itee.uq.edu.au
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive :
http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/


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CONFIG_UCLINUX=y
CONFIG_UID16=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y

CONFIG_EXPERIMENTAL=y

CONFIG_MODULES=y
CONFIG_MICROBLAZE=y

CONFIG_UCLINUX_AUTO=y
HZ=100
CONFIG_XILINX_ERAM_START=0xfe000000
CONFIG_XILINX_ERAM_SIZE=0x01000000
CONFIG_XILINX_FLASH_START=0xff000000
CONFIG_XILINX_FLASH_SIZE=0x00800000
CONFIG_XILINX_LMB_START=0x00000000
CONFIG_XILINX_LMB_SIZE=0x00004000
CONFIG_XILINX_CPU_CLOCK_FREQ=25000000
CONFIG_XILINX_MICROBLAZE0_INSTANCE="microblaze_0
"
CONFIG_XILINX_MICROBLAZE0_FAMILY="spartan3
"
CONFIG_XILINX_MICROBLAZE0_INSTANCE="microblaze_0
"
CONFIG_XILINX_MICROBLAZE0_D_OPB=1
CONFIG_XILINX_MICROBLAZE0_D_LMB=1
CONFIG_XILINX_MICROBLAZE0_I_OPB=1
CONFIG_XILINX_MICROBLAZE0_I_LMB=1
CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
CONFIG_XILINX_MICROBLAZE0_USE_DIV=1
CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
CONFIG_XILINX_MICROBLAZE0_UNALIGNED_EXCEPTIONS=0
CONFIG_XILINX_MICROBLAZE0_ILL_OPCODE_EXCEPTION=0
CONFIG_XILINX_MICROBLAZE0_IOPB_BUS_EXCEPTION=0
CONFIG_XILINX_MICROBLAZE0_DOPB_BUS_EXCEPTION=0
CONFIG_XILINX_MICROBLAZE0_DIV_ZERO_EXCEPTION=0
CONFIG_XILINX_MICROBLAZE0_DEBUG_ENABLED=1
CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_PBRK=2
CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK=1
CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK=1
CONFIG_XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE=0
CONFIG_XILINX_MICROBLAZE0_EDGE_IS_POSITIVE=1
CONFIG_XILINX_MICROBLAZE0_FSL_LINKS=1
CONFIG_XILINX_MICROBLAZE0_FSL_DATA_SIZE=32
CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR=0x80000000
CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR=0x81FFFFFF
CONFIG_XILINX_MICROBLAZE0_USE_ICACHE=0
CONFIG_XILINX_MICROBLAZE0_ALLOW_ICACHE_WR=1
CONFIG_XILINX_MICROBLAZE0_ADDR_TAG_BITS=11
CONFIG_XILINX_MICROBLAZE0_CACHE_BYTE_SIZE=16384
CONFIG_XILINX_MICROBLAZE0_ICACHE_USE_FSL=0
CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR=0x80000000
CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR=0x81FFFFFF
CONFIG_XILINX_MICROBLAZE0_USE_DCACHE=0
CONFIG_XILINX_MICROBLAZE0_ALLOW_DCACHE_WR=1
CONFIG_XILINX_MICROBLAZE0_DCACHE_ADDR_TAG=11
CONFIG_XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE=16384
CONFIG_XILINX_MICROBLAZE0_DCACHE_USE_FSL=0
CONFIG_XILINX_MICROBLAZE0_INSTANCE="microblaze_0
"
CONFIG_XILINX_MICROBLAZE0_HW_VER="3.00.a
"
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE="dlmb_cntlr
"
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR=0x00000000
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR=0x00003FFF
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_MASK=0x40000000
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH=32
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH=32
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE="dlmb_cntlr
"
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER="1.00.b
"
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE="ilmb_cntlr
"
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR=0x00000000
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR=0x00003FFF
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_MASK=0x40000000
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH=32
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH=32
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE="ilmb_cntlr
"
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER="1.00.b
"
CONFIG_XILINX_EMC_0_INSTANCE="sram_flash
"
CONFIG_XILINX_EMC_0_NUM_BANKS_MEM=1
CONFIG_XILINX_EMC_0_INCLUDE_NEGEDGE_IOREGS=0
CONFIG_XILINX_EMC_0_BASEADDR=0xFFFF0000
CONFIG_XILINX_EMC_0_HIGHADDR=0xFFFF01FF
CONFIG_XILINX_EMC_0_MEM0_BASEADDR=0xFF800000
CONFIG_XILINX_EMC_0_MEM0_HIGHADDR=0xFFBFFFFF
CONFIG_XILINX_EMC_0_MEM1_BASEADDR=0xFF000000
CONFIG_XILINX_EMC_0_MEM1_HIGHADDR=0xFF7FFFFF
CONFIG_XILINX_EMC_0_MEM2_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_EMC_0_MEM2_HIGHADDR=0x00000000
CONFIG_XILINX_EMC_0_MEM3_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_EMC_0_MEM3_HIGHADDR=0x00000000
CONFIG_XILINX_EMC_0_MEM4_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_EMC_0_MEM4_HIGHADDR=0x00000000
CONFIG_XILINX_EMC_0_MEM5_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_EMC_0_MEM5_HIGHADDR=0x00000000
CONFIG_XILINX_EMC_0_MEM6_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_EMC_0_MEM6_HIGHADDR=0x00000000
CONFIG_XILINX_EMC_0_MEM7_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_EMC_0_MEM7_HIGHADDR=0x00000000
CONFIG_XILINX_EMC_0_MEM0_WIDTH=16
CONFIG_XILINX_EMC_0_MEM1_WIDTH=32
CONFIG_XILINX_EMC_0_MEM2_WIDTH=32
CONFIG_XILINX_EMC_0_MEM3_WIDTH=32
CONFIG_XILINX_EMC_0_MEM4_WIDTH=32
CONFIG_XILINX_EMC_0_MEM5_WIDTH=32
CONFIG_XILINX_EMC_0_MEM6_WIDTH=32
CONFIG_XILINX_EMC_0_MEM7_WIDTH=32
CONFIG_XILINX_EMC_0_MAX_MEM_WIDTH=16
CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_0=0
CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_1=1
CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_2=1
CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_3=1
CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_4=1
CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_5=1
CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_6=1
CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_7=1
CONFIG_XILINX_EMC_0_SYNCH_MEM_0=0
CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_0=2
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_0=150000
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_0=55000
CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_0=70000
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_0=150000
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_0=55000
CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_0=15000
CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_0=35000
CONFIG_XILINX_EMC_0_SYNCH_MEM_1=0
CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_1=2
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_1=150000
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_1=55000
CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_1=70000
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_1=150000
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_1=55000
CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_1=15000
CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_1=35000
CONFIG_XILINX_EMC_0_SYNCH_MEM_2=0
CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_2=2
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_2=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_2=0
CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_2=0
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_2=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_2=0
CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_2=0
CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_2=0
CONFIG_XILINX_EMC_0_SYNCH_MEM_3=0
CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_3=2
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_3=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_3=0
CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_3=0
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_3=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_3=0
CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_3=0
CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_3=0
CONFIG_XILINX_EMC_0_SYNCH_MEM_4=0
CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_4=2
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_4=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_4=0
CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_4=0
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_4=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_4=0
CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_4=0
CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_4=0
CONFIG_XILINX_EMC_0_SYNCH_MEM_5=0
CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_5=2
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_5=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_5=0
CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_5=0
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_5=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_5=0
CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_5=0
CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_5=0
CONFIG_XILINX_EMC_0_SYNCH_MEM_6=0
CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_6=2
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_6=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_6=0
CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_6=0
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_6=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_6=0
CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_6=0
CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_6=0
CONFIG_XILINX_EMC_0_SYNCH_MEM_7=0
CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_7=2
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_7=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_7=0
CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_7=0
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_7=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_7=0
CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_7=0
CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_7=0
CONFIG_XILINX_EMC_0_OPB_DWIDTH=32
CONFIG_XILINX_EMC_0_OPB_AWIDTH=32
CONFIG_XILINX_EMC_0_OPB_CLK_PERIOD_PS=40000
CONFIG_XILINX_EMC_0_DEV_BLK_ID=1
CONFIG_XILINX_EMC_0_DEV_MIR_ENABLE=1
CONFIG_XILINX_EMC_0_INSTANCE="sram_flash
"
CONFIG_XILINX_EMC_0_HW_VER="1.10.b
"
CONFIG_XILINX_UARTLITE_0_INSTANCE="console_uart
"
CONFIG_XILINX_UARTLITE_0_BASEADDR=0xFFFF2000
CONFIG_XILINX_UARTLITE_0_HIGHADDR=0xFFFF20FF
CONFIG_XILINX_UARTLITE_0_OPB_DWIDTH=32
CONFIG_XILINX_UARTLITE_0_OPB_AWIDTH=32
CONFIG_XILINX_UARTLITE_0_DATA_BITS=8
CONFIG_XILINX_UARTLITE_0_CLK_FREQ=25000000
CONFIG_XILINX_UARTLITE_0_BAUDRATE=9600
CONFIG_XILINX_UARTLITE_0_USE_PARITY=0
CONFIG_XILINX_UARTLITE_0_ODD_PARITY=0
CONFIG_XILINX_UARTLITE_0_INSTANCE="console_uart
"
CONFIG_XILINX_UARTLITE_0_HW_VER="1.00.b
"
CONFIG_XILINX_UARTLITE_0_IRQ=1
CONFIG_XILINX_INTC_0_INSTANCE="system_intc
"
CONFIG_XILINX_INTC_0_FAMILY="spartan3
"
CONFIG_XILINX_INTC_0_Y=0
CONFIG_XILINX_INTC_0_X=0
CONFIG_XILINX_INTC_0_U_SET="intc
"
CONFIG_XILINX_INTC_0_OPB_AWIDTH=32
CONFIG_XILINX_INTC_0_OPB_DWIDTH=32
CONFIG_XILINX_INTC_0_BASEADDR=0xFFFF3000
CONFIG_XILINX_INTC_0_HIGHADDR=0xFFFF30FF
CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS=3
CONFIG_XILINX_INTC_0_KIND_OF_INTR=0x00000002
CONFIG_XILINX_INTC_0_KIND_OF_EDGE=0x00000002
CONFIG_XILINX_INTC_0_KIND_OF_LVL=0x00000005
CONFIG_XILINX_INTC_0_HAS_IPR=1
CONFIG_XILINX_INTC_0_HAS_SIE=1
CONFIG_XILINX_INTC_0_HAS_CIE=1
CONFIG_XILINX_INTC_0_HAS_IVR=1
CONFIG_XILINX_INTC_0_IRQ_IS_LEVEL=1
CONFIG_XILINX_INTC_0_IRQ_ACTIVE=1
CONFIG_XILINX_INTC_0_INSTANCE="system_intc
"
CONFIG_XILINX_INTC_0_HW_VER="1.00.c
"
CONFIG_XILINX_TIMER_0_INSTANCE="system_timer
"
CONFIG_XILINX_TIMER_0_FAMILY="spartan3
"
CONFIG_XILINX_TIMER_0_COUNT_WIDTH=32
CONFIG_XILINX_TIMER_0_ONE_TIMER_ONLY=0
CONFIG_XILINX_TIMER_0_TRIG0_ASSERT=1
CONFIG_XILINX_TIMER_0_TRIG1_ASSERT=1
CONFIG_XILINX_TIMER_0_GEN0_ASSERT=1
CONFIG_XILINX_TIMER_0_GEN1_ASSERT=1
CONFIG_XILINX_TIMER_0_OPB_AWIDTH=32
CONFIG_XILINX_TIMER_0_OPB_DWIDTH=32
CONFIG_XILINX_TIMER_0_BASEADDR=0xFFFF1000
CONFIG_XILINX_TIMER_0_HIGHADDR=0xFFFF10FF
CONFIG_XILINX_TIMER_0_INSTANCE="system_timer
"
CONFIG_XILINX_TIMER_0_HW_VER="1.00.b
"
CONFIG_XILINX_TIMER_0_IRQ=0
CONFIG_XILINX_GPIO_0_INSTANCE="system_gpio
"
CONFIG_XILINX_GPIO_0_BASEADDR=0xFFFF5000
CONFIG_XILINX_GPIO_0_HIGHADDR=0xFFFF50FF
CONFIG_XILINX_GPIO_0_OPB_DWIDTH=32
CONFIG_XILINX_GPIO_0_OPB_AWIDTH=32
CONFIG_XILINX_GPIO_0_GPIO_WIDTH=24
CONFIG_XILINX_GPIO_0_ALL_INPUTS=0
CONFIG_XILINX_GPIO_0_IS_BIDIR=1
CONFIG_XILINX_GPIO_0_DOUT_DEFAULT=0x00000000
CONFIG_XILINX_GPIO_0_TRI_DEFAULT=0xFFFFFFFF
CONFIG_XILINX_GPIO_0_IS_DUAL=0
CONFIG_XILINX_GPIO_0_ALL_INPUTS_2=0
CONFIG_XILINX_GPIO_0_IS_BIDIR_2=1
CONFIG_XILINX_GPIO_0_DOUT_DEFAULT_2=0x00000000
CONFIG_XILINX_GPIO_0_TRI_DEFAULT_2=0xFFFFFFFF
CONFIG_XILINX_GPIO_0_INSTANCE="system_gpio
"
CONFIG_XILINX_GPIO_0_HW_VER="2.00.a
"
CONFIG_XILINX_ETHERNET_0_INSTANCE="ethernet
"
CONFIG_XILINX_ETHERNET_0_DEV_BLK_ID=1
CONFIG_XILINX_ETHERNET_0_DEV_MIR_ENABLE=1
CONFIG_XILINX_ETHERNET_0_BASEADDR=0xC0000000
CONFIG_XILINX_ETHERNET_0_HIGHADDR=0xC0003FFF
CONFIG_XILINX_ETHERNET_0_RESET_PRESENT=1
CONFIG_XILINX_ETHERNET_0_INCLUDE_DEV_PENCODER=1
CONFIG_XILINX_ETHERNET_0_DMA_PRESENT=1
CONFIG_XILINX_ETHERNET_0_DMA_INTR_COALESCE=1
CONFIG_XILINX_ETHERNET_0_OPB_AWIDTH=32
CONFIG_XILINX_ETHERNET_0_OPB_DWIDTH=32
CONFIG_XILINX_ETHERNET_0_OPB_CLK_PERIOD_PS=40000
CONFIG_XILINX_ETHERNET_0_FAMILY="spartan3
"
CONFIG_XILINX_ETHERNET_0_IPIF_FIFO_DEPTH=32768
CONFIG_XILINX_ETHERNET_0_SOURCE_ADDR_INSERT_EXIST=1
CONFIG_XILINX_ETHERNET_0_PAD_INSERT_EXIST=1
CONFIG_XILINX_ETHERNET_0_FCS_INSERT_EXIST=1
CONFIG_XILINX_ETHERNET_0_MAFIFO_DEPTH=16
CONFIG_XILINX_ETHERNET_0_HALF_DUPLEX_EXIST=1
CONFIG_XILINX_ETHERNET_0_ERR_COUNT_EXIST=1
CONFIG_XILINX_ETHERNET_0_MII_EXIST=1
CONFIG_XILINX_ETHERNET_0_INSTANCE="ethernet
"
CONFIG_XILINX_ETHERNET_0_HW_VER="1.00.m
"
CONFIG_XILINX_ETHERNET_0_IRQ=2
CONFIG_XILINX_SDRAM_0_INSTANCE="opb_sdram_0
"
CONFIG_XILINX_SDRAM_0_INCLUDE_BURST_SUPPORT=1
CONFIG_XILINX_SDRAM_0_INCLUDE_HIGHSPEED_PIPE=1
CONFIG_XILINX_SDRAM_0_USE_POSEDGE_OUTREGS=0
CONFIG_XILINX_SDRAM_0_FAMILY="spartan3
"
CONFIG_XILINX_SDRAM_0_SDRAM_TMRD=2
CONFIG_XILINX_SDRAM_0_SDRAM_TWR=15000
CONFIG_XILINX_SDRAM_0_SDRAM_TCCD=1
CONFIG_XILINX_SDRAM_0_SDRAM_TRAS=37000
CONFIG_XILINX_SDRAM_0_SDRAM_TRC=63000
CONFIG_XILINX_SDRAM_0_SDRAM_TRFC=75000
CONFIG_XILINX_SDRAM_0_SDRAM_TRCD=15000
CONFIG_XILINX_SDRAM_0_SDRAM_TRRD=14000
CONFIG_XILINX_SDRAM_0_SDRAM_TRP=15000
CONFIG_XILINX_SDRAM_0_SDRAM_TREF=64
CONFIG_XILINX_SDRAM_0_SDRAM_REFRESH_NUMROWS=4096
CONFIG_XILINX_SDRAM_0_SDRAM_CAS_LAT=2
CONFIG_XILINX_SDRAM_0_SDRAM_DWIDTH=32
CONFIG_XILINX_SDRAM_0_SDRAM_AWIDTH=12
CONFIG_XILINX_SDRAM_0_SDRAM_COL_AWIDTH=8
CONFIG_XILINX_SDRAM_0_SDRAM_BANK_AWIDTH=2
CONFIG_XILINX_SDRAM_0_SDRAM_TREFI=15625000
CONFIG_XILINX_SDRAM_0_BASEADDR=0xFE000000
CONFIG_XILINX_SDRAM_0_HIGHADDR=0xFEFFFFFF
CONFIG_XILINX_SDRAM_0_OPB_DWIDTH=32
CONFIG_XILINX_SDRAM_0_OPB_AWIDTH=32
CONFIG_XILINX_SDRAM_0_OPB_CLK_PERIOD_PS=40000
CONFIG_XILINX_SDRAM_0_SIM_INIT_TIME_PS=100000000
CONFIG_XILINX_SDRAM_0_INSTANCE="opb_sdram_0
"
CONFIG_XILINX_SDRAM_0_HW_VER="1.00.d
"
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES=2
CONFIG_XILINX_TIMER_NUM_INSTANCES=1
CONFIG_XILINX_EMC_NUM_INSTANCES=1
CONFIG_XILINX_INTC_NUM_INSTANCES=1
CONFIG_XILINX_UARTLITE_NUM_INSTANCES=1
CONFIG_XILINX_SDRAM_NUM_INSTANCES=1
CONFIG_XILINX_ETHERNET_NUM_INSTANCES=1
CONFIG_XILINX_GPIO_NUM_INSTANCES=1
CONFIG_XILINX_GPIO=y
CONFIG_XILINX_ENET=y
CONFIG_ZERO_BSS=y

CONFIG_NET=y
CONFIG_KCORE_ELF=y
CONFIG_BINFMT_FLAT=y
CONFIG_BINFMT_ZFLAT=y

CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y

CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_GEN_PROBE=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_RAM=y

CONFIG_MTD_MBVANILLA=y
CONFIG_FLASH8MB=y




CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=4096

CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y


















CONFIG_RAMFS=y
CONFIG_PROC_FS=y
CONFIG_ROMFS_FS=y
CONFIG_EXT2_FS=y

CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_SUNRPC=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y





CONFIG_FULLDEBUG=y


CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y

References:
- Re: [microblaze-uclinux] Kernel crash debug: No code generated for'get_romfs_base()' function?
  - From: Greg Ungerer

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