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Re: [microblaze-uclinux] Kernel hangs after mount filesystem on CF card
On Thursday 17 March 2005 20:55, you wrote:
> Are you sure that the CF interrupt is correctly connected in your
> hardware design?
>
I don't think it's an interrupt issue since /proc/interrupts reports a valid
number (not 0) and the read operations works (I tried to copy a file from
the partition mounted readonly).
However give a look at my sytem.mhs file (in the attachment) and let me know
if you find something wrong, please.
I use the systemace board 25MHz clock for the opb_systemace core and multiply
it by 4/3 to obtain the system 33MHz clock. I read in datasheets that OPB
clock should be greater than systemace clock.
[ ... boot log ]
# cat /proc/partitions
major minor #blocks name rio rmerge rsect ruse wio wmerge wsect wuse
running use aveq
254 0 125440 xsysace/disc0/disc 1 3 8 40 0 0 0 0 0 40 40
254 1 15717 xsysace/disc0/part1 0 0 0 0 0 0 0 0 0 0 0
254 2 109616 xsysace/disc0/part2 0 0 0 0 0 0 0 0 0 0 0
# mount -r /dev/xsysace/disc0/part2 /mnt
# cd /mnt
# cp minicom.cap /tmp
# cat /proc/interrupts
CPU0
0: 16958 XINTC timer
1: 909 XINTC Microblaze UARTlite
2: 429 XINTC System ACE
ERR: 0
# cat /proc/partitions
major minor #blocks name rio rmerge rsect ruse wio wmerge wsect wuse
running use aveq
254 0 125440 xsysace/disc0/disc 8 5 26 160 0 0 0 0 0 160 160
254 1 15717 xsysace/disc0/part1 0 0 0 0 0 0 0 0 0 0 0
254 2 109616 xsysace/disc0/part2 7 2 18 120 0 0 0 0 0 120 120
# cd /
# umount /mnt
# mount /dev/xsysace/disc0/part2 /mnt
System hangs here!!!!!!!
PARAMETER VERSION = 2.1.0
PORT sys_clk_pin = dcm_clk_s, DIR = I
PORT sys_rst_pin = sys_rst, DIR = I
PORT sdram_clk_in = sdram_clkfb, DIR = I
PORT opbsdram_clk = opbsdram_clk, DIR = O
PORT opbsdram_cke = opbsdram_cke, DIR = O
PORT opbsdram_cs = opbsdram_cs, DIR = O
PORT opbsdram_ras = opbsdram_ras, DIR = O
PORT opbsdram_cas = opbsdram_cas, DIR = O
PORT opbsdram_we = opbsdram_we, DIR = O
PORT opbsdram_dqm = opbsdram_dqm, VEC = [0:1], DIR = O
PORT opbsdram_baddr = opbsdram_baddr, VEC = [0:1], DIR = O
PORT opbsdram_addr = opbsdram_addr, VEC = [0:12], DIR = O
PORT opbsdram_dq = opbsdram_dq, VEC = [0:15], DIR = IO
PORT sdclk_gen_LOCKED = sdclk_gen_LOCKED, DIR = O
PORT console_uart_rx = console_uart_rx, DIR = I
PORT console_uart_tx = console_uart_tx, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, VEC = [6:0], DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, VEC = [15:0], DIR = IO
PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
# Sub Components
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 3.00.a
PARAMETER C_USE_BARREL = 1
PARAMETER C_USE_DIV = 1
PARAMETER C_USE_MSR_INSTR = 1
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
PARAMETER C_USE_ICACHE = 1
PARAMETER C_ICACHE_BASEADDR = 0x80000000
PARAMETER C_ICACHE_HIGHADDR = 0x81ffffff
PARAMETER C_CACHE_BYTE_SIZE = 8192
PARAMETER C_ADDR_TAG_BITS = 12
PARAMETER C_USE_DCACHE = 1
PARAMETER C_DCACHE_BASEADDR = 0x80000000
PARAMETER C_DCACHE_HIGHADDR = 0x81ffffff
PARAMETER C_DCACHE_BYTE_SIZE = 8192
PARAMETER C_DCACHE_ADDR_TAG = 12
PARAMETER C_FSL_LINKS = 1
BUS_INTERFACE SFSL0 = download_link
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
PORT CLK = sys_clk
PORT INTERRUPT = interrupt
END
#dcm_mul take 25MHz oscillator clock on SAM board and multiply it 4/3 to obtain system 33MHz
#internal feedback for systemace 25MHz clock (needed?)
BEGIN dcm_module
PARAMETER INSTANCE = dcm_mul
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_CLKFX_MULTIPLY = 4
PARAMETER C_CLKFX_DIVIDE = 3
PARAMETER C_CLKIN_PERIOD = 40.00000
PARAMETER C_CLKFX_BUF = TRUE
PARAMETER C_CLK0_BUF = TRUE
PORT RST = net_gnd
PORT CLKIN = dcm_clk_s
PORT CLKFX = dcm_clk_mul
PORT CLKFB = ace_clk
PORT CLK0 = ace_clk
END
#internal feedback for 33MHz system clock
BEGIN dcm_module
PARAMETER INSTANCE = dcm_intfb
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 30.00000
PORT RST = net_gnd
PORT CLKIN = dcm_clk_mul
PORT CLKFB = sys_clk
PORT CLK0 = sys_clk
END
#external feedback for 33MHz sdram clock
BEGIN dcm_module
PARAMETER INSTANCE = dcm_extfb
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_CLKIN_PERIOD = 30.00000
PARAMETER C_CLK0_BUF = FALSE
PARAMETER C_CLKFB_BUF = TRUE
PORT RST = net_gnd
PORT CLKIN = dcm_clk_mul
PORT CLKFB = sdram_clkfb
PORT CLK0 = sdram_clk_out
PORT LOCKED = sdclk_gen_LOCKED
END
BEGIN opb_sysace
PARAMETER INSTANCE = SysACE_CompactFlash
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0xfffe0000
PARAMETER C_HIGHADDR = 0xfffeffff
BUS_INTERFACE SOPB = mb_opb
PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA
PORT SysACE_CLK = ace_clk
PORT OPB_Clk = sys_clk
PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ
END
BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 0
PARAMETER C_UART_WIDTH = 8
PARAMETER C_WRITE_FSL_PORTS = 1
PARAMETER C_BASEADDR = 0xFFFFC000
PARAMETER C_HIGHADDR = 0xFFFFC0FF
BUS_INTERFACE MFSL0 = download_link
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk
END
BEGIN fsl_v20
PARAMETER INSTANCE = download_link
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst
PORT FSL_Clk = sys_clk
END
BEGIN opb_uartlite
PARAMETER INSTANCE = console_uart
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 57600
PARAMETER C_DATA_BITS = 8
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 0
PARAMETER C_CLK_FREQ = 33_333_334
PARAMETER C_BASEADDR = 0xFFFF2000
PARAMETER C_HIGHADDR = 0xFFFF20FF
BUS_INTERFACE SOPB = mb_opb
PORT Interrupt = console_uart_interrupt
PORT OPB_Clk = sys_clk
PORT RX = console_uart_rx
PORT TX = console_uart_tx
END
BEGIN opb_intc
PARAMETER INSTANCE = system_intc
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0xffff3000
PARAMETER C_HIGHADDR = 0xffff30ff
BUS_INTERFACE SOPB = mb_opb
PORT Irq = interrupt
PORT OPB_Clk = sys_clk
PORT Intr = SysACE_CompactFlash_SysACE_IRQ & console_uart_interrupt & timer_interrupt
END
BEGIN opb_timer
PARAMETER INSTANCE = system_timer
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0xffff1000
PARAMETER C_HIGHADDR = 0xffff10ff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk
PORT Interrupt = timer_interrupt
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003FFF
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = conn_0
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003FFF
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = conn_1
END
BEGIN bram_block
PARAMETER INSTANCE = bram
PARAMETER HW_VER = 1.00.a
PARAMETER C_MEMSIZE = 16384
BUS_INTERFACE PORTA = conn_0
BUS_INTERFACE PORTB = conn_1
END
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 0
PORT OPB_Clk = sys_clk
PORT SYS_Rst = sys_rst
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT LMB_Clk = sys_clk
PORT SYS_Rst = sys_rst
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT LMB_Clk = sys_clk
PORT SYS_Rst = sys_rst
END
BEGIN opb_sdram
PARAMETER INSTANCE = sdram_controller
PARAMETER HW_VER = 1.00.e
PARAMETER C_OPB_CLK_PERIOD_PS = 30000
PARAMETER C_INCLUDE_BURST_SUPPORT = 0
PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 1
PARAMETER C_SDRAM_BANK_AWIDTH = 2
PARAMETER C_SDRAM_AWIDTH = 13
PARAMETER C_SDRAM_COL_AWIDTH = 9
PARAMETER C_SDRAM_TRAS = 45000
PARAMETER C_SDRAM_DWIDTH = 16
PARAMETER C_SDRAM_TRC = 66000
PARAMETER C_BASEADDR = 0x80000000
PARAMETER C_HIGHADDR = 0x81ffffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk
PORT SDRAM_Clk_in = sdram_clk_out
PORT SDRAM_Clk = opbsdram_clk
PORT SDRAM_CKE = opbsdram_cke
PORT SDRAM_CSn = opbsdram_cs
PORT SDRAM_RASn = opbsdram_ras
PORT SDRAM_CASn = opbsdram_cas
PORT SDRAM_WEn = opbsdram_we
PORT SDRAM_DQM = opbsdram_dqm
PORT SDRAM_BankAddr = opbsdram_baddr
PORT SDRAM_Addr = opbsdram_addr
PORT SDRAM_DQ = opbsdram_dq
END