[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[microblaze-uclinux] Problem downloading kernel

To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] Problem downloading kernel
From: Bertrand Rousseau <bertrand.rousseau@xxxxxxxxx>
Date: Fri, 8 Apr 2005 15:59:32 +0200
Domainkey-signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:reply-to:to:subject:mime-version:content-type:content-transfer-encoding; b=Jh/q7Sn24r5wgjzfA0Y3J7BtJ3BLUKNsdz/cLHAvoS82pVB3W+XtaTkMDxc+kFtxDoOzCtud36/oLhTCl5D3tcI8lZIhVxtUx8bUC2oDdhtLDW2vlEb4ZPdSHMRo+oPmrpb/7E98Rxu08CFmOkHATRpLRsOt65WFB/iIB/uh3dE=
Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxx
Hi everyone,

I have some problems downloading the kernel into the DDR memory. I'm
using the XMD 'dow -data' command in order to do it. And xmd connects
fine to the microblaze:

seraphin:~/TFE/no_ethernet_uclinux> xmd
WARNING: fr_BE:fr_FR:fr:en_GB:en is not supported as a language. 
Using usenglish.
Xilinx Microprocessor Debug (XMD) Engine
Xilinx EDK 6.3 Build EDK_Gmm.12.3
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

XMD%
XMD% xload mhs system.mhs
Loading MHS File..
Processor(s) in System ::

Microblaze(1) : microblaze_0
Address Map for Processor microblaze_0
  (0x00000000-0x00003fff) dlmb_cntlr    dlmb
  (0x00000000-0x00003fff) ilmb_cntlr    ilmb
  (0x84000000-0x8400ffff) opb_timer_1   mb_opb
  (0x84010000-0x8401ffff) opb_intc_0    mb_opb
  (0x84020000-0x8402ffff) debug_module  mb_opb
  (0x84030000-0x8403ffff) RS232 mb_opb
  (0x84040000-0x8404ffff) Push_Button_SW4       mb_opb
  (0x84050000-0x8405ffff) LEDs  mb_opb
  (0x84060000-0x8406ffff) DIP_Switches  mb_opb
  (0x84800000-0x84ffffff) FLASH mb_opb
  (0x86000000-0x87ffffff) DDR_SDRAM_16Mx16      mb_opb

XMD% connect mb mdm
Connecting to cable (Parallel Port - parport0).
  WinDriver v6.23 Jungo (c) 1997 - 2004 Build Date: Nov 17 2004 X86 11:07:00.
  parport0: baseAddress=0x378, ecpAddress=0x778
  LPT base address = 0378h.
  ECP base address = 0778h.
  ECP hardware is detected.
Cable connection established.
Connecting to cable (Parallel Port - parport0) in ECP mode.
 Module xpc4drvr is not loaded.
Cable connection failed.
Connecting to cable (Parallel Port - parport0).
  WinDriver v6.23 Jungo (c) 1997 - 2004 Build Date: Nov 17 2004 X86 11:07:00.
  LPT base address = 0378h.
  ECP base address = 0778h.
Cable connection established.
ECP port test failed. Using download cable in compatibility mode.

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       05057093          16        XCF08P
 2       0167c093          10        XC4VLX25
Assuming, Device No: 2 contains the MicroBlaze system
Connected to the JTAG MicroBlaze Debug Module (MDM)
No of processors = 1

MicroBlaze Processor 1 Configuration :
-------------------------------------
Version............................3.00.a
No of PC Breakpoints...............2
No of Read Addr/Data Watchpoints...1
No of Write Addr/Data Watchpoints..1
Instruction Cache Support..........off
Data Cache Support.................off
MBsfsl(0)-MDMmfsl(0) Connected..........Yes
JTAG MDM Connected to MicroBlaze 1
Connected to "mb" target. id = 0
Starting GDB server for "mb" target (id = 0) at TCP port no 1234
XMD%

But once it is done, I get this message when I run the program:

XMD% dow -data /home/bertrand/TFE/uClinux-dist/images/image.bin 0x86000000
XMD% con 0x86000000
Processor started. Type "stop" to stop processor
RUNNING>
XMD%
ERROR:EDK - MicroBlaze Pipeline Stalled executing Instruction at >> PC:
   0x00000000
   Try Resetting the Processor to Continue..

So I can't even check if the download was right. I'm not sure, but it
seems that the configuration of my FPGA is completely broken after
that, because when I try basic command after the download I alway
these errors:

XMD% rrd
 Target Cannot perform the Operation

XMD% mrd 0x86000000
 Target Cannot perform the Operation

Could anyone help me to find what the problem is? This problem is a
real nightmare for me now. Oh, and I'm using EDK 6.3i under linux.

Here are my system.mhs and system.mss files:

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 6.3 Build EDK_Gmm.12.3
# Wed Apr  6 00:27:38 2005
# Target Board:  Avnet Avnet Virtex-4 LX Evaluation Board Rev 1.0
# Family:	 virtex4
# Device:	 XC4VLX25
# Package:	 FF668
# Speed Grade:	 -10
# Processor: Microblaze
# System clock frequency: 100.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory :  16 KB
# Total Off Chip Memory :  32 MB
# - DDR_SDRAM_16Mx16 =  32 MB
# ##############################################################################


 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = IN
 PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = OUT
 PORT fpga_0_LEDs_GPIO_IO_pin = fpga_0_LEDs_GPIO_IO, DIR = INOUT, VEC = [0:7]
 PORT fpga_0_Push_Button_SW4_GPIO_in_pin =
fpga_0_Push_Button_SW4_GPIO_in, DIR = IN, VEC = [0:0]
 PORT fpga_0_DIP_Switches_GPIO_in_pin = fpga_0_DIP_Switches_GPIO_in,
DIR = IN, VEC = [0:7]
 PORT fpga_0_DDR_SDRAM_16Mx16_DDR_Clk_pin =
fpga_0_DDR_SDRAM_16Mx16_DDR_Clk, DIR = OUT, VEC = [0:1]
 PORT fpga_0_DDR_SDRAM_16Mx16_DDR_Clkn_pin =
fpga_0_DDR_SDRAM_16Mx16_DDR_Clkn, DIR = OUT, VEC = [0:1]
 PORT fpga_0_DDR_SDRAM_16Mx16_DDR_Addr_pin =
fpga_0_DDR_SDRAM_16Mx16_DDR_Addr, DIR = OUT, VEC = [0:12]
 PORT fpga_0_DDR_SDRAM_16Mx16_DDR_BankAddr_pin =
fpga_0_DDR_SDRAM_16Mx16_DDR_BankAddr, DIR = OUT, VEC = [0:1]
 PORT fpga_0_DDR_SDRAM_16Mx16_DDR_CASn_pin =
fpga_0_DDR_SDRAM_16Mx16_DDR_CASn, DIR = OUT
 PORT fpga_0_DDR_SDRAM_16Mx16_DDR_CKE_pin =
fpga_0_DDR_SDRAM_16Mx16_DDR_CKE, DIR = OUT
 PORT fpga_0_DDR_SDRAM_16Mx16_DDR_CSn_pin =
fpga_0_DDR_SDRAM_16Mx16_DDR_CSn, DIR = OUT
 PORT fpga_0_DDR_SDRAM_16Mx16_DDR_RASn_pin =
fpga_0_DDR_SDRAM_16Mx16_DDR_RASn, DIR = OUT
 PORT fpga_0_DDR_SDRAM_16Mx16_DDR_WEn_pin =
fpga_0_DDR_SDRAM_16Mx16_DDR_WEn, DIR = OUT
 PORT fpga_0_DDR_SDRAM_16Mx16_DDR_DM_pin =
fpga_0_DDR_SDRAM_16Mx16_DDR_DM, DIR = OUT, VEC = [0:1]
 PORT fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin =
fpga_0_DDR_SDRAM_16Mx16_DDR_DQS, DIR = INOUT, VEC = [0:1]
 PORT fpga_0_DDR_SDRAM_16Mx16_DDR_DQ_pin =
fpga_0_DDR_SDRAM_16Mx16_DDR_DQ, DIR = INOUT, VEC = [0:15]
 PORT fpga_0_FLASH_Mem_DQ_pin = fpga_0_FLASH_Mem_DQ, VEC = [0:31], DIR = INOUT
 PORT fpga_0_FLASH_Mem_A_pin = fpga_0_FLASH_Mem_A, VEC = [9:30], DIR = OUT
 PORT fpga_0_FLASH_Mem_WEN_pin = fpga_0_FLASH_Mem_WEN, DIR = OUT
 PORT fpga_0_FLASH_Mem_OEN_pin = fpga_0_FLASH_Mem_OEN, VEC = [0:0], DIR = OUT
 PORT fpga_0_FLASH_Mem_CEN_pin = fpga_0_FLASH_Mem_CEN, VEC = [0:0], DIR = OUT
 PORT fpga_0_FLASH_Mem_RPN_pin = fpga_0_FLASH_Mem_RPN, DIR = OUT
 PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = IN
 PORT sys_clk_pin = dcm_clk_s, DIR = IN
 PORT sys_rst_pin = sys_rst_s, DIR = IN


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_DIV = 1
 PARAMETER C_USE_MSR_INSTR = 1
 PARAMETER C_FSL_LINKS = 1
 BUS_INTERFACE SFSL0 = download_link
  BUS_INTERFACE DLMB = dlmb
  BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 PORT CLK = sys_clk_s
 PORT DBG_CAPTURE = DBG_CAPTURE_s
 PORT DBG_CLK = DBG_CLK_s
 PORT DBG_REG_EN = DBG_REG_EN_s
 PORT DBG_TDI = DBG_TDI_s
 PORT DBG_TDO = DBG_TDO_s
 PORT DBG_UPDATE = DBG_UPDATE_s
 PORT Interrupt = Interrupt
END

BEGIN opb_v20
 PARAMETER INSTANCE = mb_opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_rst_s
 PORT OPB_Clk = sys_clk_s
END

BEGIN opb_mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.01.a
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
  PARAMETER C_BASEADDR = 0x84020000
  PARAMETER C_HIGHADDR = 0x8402ffff
 PARAMETER C_WRITE_FSL_PORTS = 1
 BUS_INTERFACE MFSL0 = download_link
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
 PORT DBG_CLK_0 = DBG_CLK_s
 PORT DBG_REG_EN_0 = DBG_REG_EN_s
 PORT DBG_TDI_0 = DBG_TDI_s
 PORT DBG_TDO_0 = DBG_TDO_s
 PORT DBG_UPDATE_0 = DBG_UPDATE_s
END

BEGIN fsl_v20
 PARAMETER INSTANCE = download_link
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT FSL_Clk = sys_clk_s
END

BEGIN lmb_v10
  PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
  PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 1.00.b
  PARAMETER C_BASEADDR = 0x00000000
  PARAMETER C_HIGHADDR = 0x00003fff
  BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 1.00.b
  PARAMETER C_BASEADDR = 0x00000000
  PARAMETER C_HIGHADDR = 0x00003fff
  BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_MEMSIZE = 16384
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN opb_uartlite
  PARAMETER INSTANCE = RS232
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_CLK_FREQ = 100000000
  PARAMETER C_BASEADDR = 0x84030000
  PARAMETER C_HIGHADDR = 0x8403ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT Interrupt = RS232_Interrupt
 PORT RX = fpga_0_RS232_RX
 PORT TX = fpga_0_RS232_TX
END

BEGIN opb_gpio
 PARAMETER INSTANCE = LEDs
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_ALL_INPUTS = 0
  PARAMETER C_BASEADDR = 0x84050000
  PARAMETER C_HIGHADDR = 0x8405ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT GPIO_IO = fpga_0_LEDs_GPIO_IO
END

BEGIN opb_gpio
 PARAMETER INSTANCE = Push_Button_SW4
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 1
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_ALL_INPUTS = 1
  PARAMETER C_BASEADDR = 0x84040000
  PARAMETER C_HIGHADDR = 0x8404ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT GPIO_in = fpga_0_Push_Button_SW4_GPIO_in
END

BEGIN opb_gpio
 PARAMETER INSTANCE = DIP_Switches
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_ALL_INPUTS = 1
  PARAMETER C_BASEADDR = 0x84060000
  PARAMETER C_HIGHADDR = 0x8406ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT GPIO_in = fpga_0_DIP_Switches_GPIO_in
END

BEGIN opb_ddr
 PARAMETER INSTANCE = DDR_SDRAM_16Mx16
 PARAMETER HW_VER = 1.10.a
 PARAMETER C_OPB_CLK_PERIOD_PS = 10000
 PARAMETER C_REG_DIMM = 0
 PARAMETER C_DDR_TMRD = 15000
 PARAMETER C_DDR_TWR = 15000
 PARAMETER C_DDR_TWTR = 1
 PARAMETER C_DDR_TRAS = 42000
 PARAMETER C_DDR_TRC = 65000
 PARAMETER C_DDR_TRFC = 75000
 PARAMETER C_DDR_TRCD = 20000
 PARAMETER C_DDR_TRRD = 15000
 PARAMETER C_DDR_TRP = 20000
 PARAMETER C_DDR_TREFC = 70300000
 PARAMETER C_DDR_TREFI = 7800000
 PARAMETER C_DDR_DWIDTH = 16
 PARAMETER C_DDR_AWIDTH = 13
 PARAMETER C_DDR_COL_AWIDTH = 9
 PARAMETER C_DDR_BANK_AWIDTH = 2
 PARAMETER C_NUM_CLK_PAIRS = 2
  PARAMETER C_MEM0_BASEADDR = 0x86000000
  PARAMETER C_MEM0_HIGHADDR = 0x87ffffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT DDR_Clk = fpga_0_DDR_SDRAM_16Mx16_DDR_Clk
 PORT DDR_Clkn = fpga_0_DDR_SDRAM_16Mx16_DDR_Clkn
 PORT DDR_Addr = fpga_0_DDR_SDRAM_16Mx16_DDR_Addr
 PORT DDR_BankAddr = fpga_0_DDR_SDRAM_16Mx16_DDR_BankAddr
 PORT DDR_CASn = fpga_0_DDR_SDRAM_16Mx16_DDR_CASn
 PORT DDR_CKE = fpga_0_DDR_SDRAM_16Mx16_DDR_CKE
 PORT DDR_CSn = fpga_0_DDR_SDRAM_16Mx16_DDR_CSn
 PORT DDR_RASn = fpga_0_DDR_SDRAM_16Mx16_DDR_RASn
 PORT DDR_WEn = fpga_0_DDR_SDRAM_16Mx16_DDR_WEn
 PORT DDR_DM = fpga_0_DDR_SDRAM_16Mx16_DDR_DM
 PORT DDR_DQS = fpga_0_DDR_SDRAM_16Mx16_DDR_DQS
 PORT DDR_DQ = fpga_0_DDR_SDRAM_16Mx16_DDR_DQ
 PORT Clk90_in = clk_90_s
 PORT Clk90_in_n = clk_90_n_s
 PORT OPB_Clk_n = sys_clk_n_s
 PORT DDR_Clk90_in = ddr_clk_90_s
 PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END

BEGIN opb_emc
 PARAMETER INSTANCE = FLASH
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_OPB_CLK_PERIOD_PS = 10000
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
 PARAMETER C_TCEDV_PS_MEM_0 = 130000
 PARAMETER C_TWC_PS_MEM_0 = 55000
 PARAMETER C_TAVDV_PS_MEM_0 = 250000
 PARAMETER C_TWP_PS_MEM_0 = 55000
 PARAMETER C_THZCE_PS_MEM_0 = 35000
 PARAMETER C_TLZWE_PS_MEM_0 = 35000
  PARAMETER C_MEM0_BASEADDR = 0x84800000
  PARAMETER C_MEM0_HIGHADDR = 0x84ffffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT Mem_A = fpga_0_FLASH_Mem_A_split
 PORT Mem_DQ = fpga_0_FLASH_Mem_DQ
 PORT Mem_WEN = fpga_0_FLASH_Mem_WEN
 PORT Mem_OEN = fpga_0_FLASH_Mem_OEN
 PORT Mem_CEN = fpga_0_FLASH_Mem_CEN
 PORT Mem_RPN = fpga_0_FLASH_Mem_RPN
END

BEGIN opb_timer
 PARAMETER INSTANCE = opb_timer_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 0
  PARAMETER C_BASEADDR = 0x84000000
  PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT Interrupt = opb_timer_1_Interrupt
END

BEGIN opb_intc
 PARAMETER INSTANCE = opb_intc_0
 PARAMETER HW_VER = 1.00.c
  PARAMETER C_BASEADDR = 0x84010000
  PARAMETER C_HIGHADDR = 0x8401ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT Irq = Interrupt
 PORT Intr = RS232_Interrupt & opb_timer_1_Interrupt
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK180_BUF = TRUE
 PARAMETER C_CLK270_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_EXT_RESET_HIGH = 1
# Bertrand: Added parameters
 PARAMETER C_CLK2X_BUF = TRUE
 PORT CLKIN = dcm_clk_s
 PORT CLK0 = sys_clk_s
 PORT CLK90 = clk_90_s
 PORT CLK180 = sys_clk_n_s
 PORT CLK270 = clk_90_n_s
 PORT CLKFB = sys_clk_s
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK270_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_EXT_RESET_HIGH = 0
# Bertrand: Added parameters
 PARAMETER C_CLK180_BUF = TRUE
 PARAMETER C_PHASE_SHIFT = 110
 PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
 PORT CLKIN = ddr_feedback_s
 PORT CLK90 = ddr_clk_90_s
 PORT CLK270 = ddr_clk_90_n_s
 PORT CLK0 = dcm_1_FB
 PORT CLKFB = dcm_1_FB
 PORT RST = dcm_0_lock
 PORT LOCKED = dcm_1_lock
END

BEGIN util_bus_split
 PARAMETER INSTANCE = FLASH_util_bus_split_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE_IN = 32
 PARAMETER C_LEFT_POS = 9
 PARAMETER C_SPLIT = 31
 PORT Sig = fpga_0_FLASH_Mem_A_split
 PORT Out1 = fpga_0_FLASH_Mem_A
END

--------------


 PARAMETER VERSION = 2.2.0


BEGIN OS
  PARAMETER OS_NAME = uclinux
 PARAMETER OS_VER = 1.00.a
 PARAMETER PROC_INSTANCE = microblaze_0
 PARAMETER main_memory = DDR_SDRAM_16Mx16
 PARAMETER main_memory_bank = 0
  PARAMETER stdout = RS232
  PARAMETER stdin = RS232
 PARAMETER flash_memory = FLASH
 PARAMETER flash_memory_bank = 0
 PARAMETER lmb_memory = dlmb_cntlr
END


BEGIN PROCESSOR
 PARAMETER DRIVER_NAME = cpu
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = microblaze_0
  PARAMETER COMPILER = mb-gcc
  PARAMETER ARCHIVER = mb-ar
 PARAMETER XMDSTUB_PERIPHERAL = debug_module
END


BEGIN DRIVER
 PARAMETER DRIVER_NAME = opbarb
 PARAMETER DRIVER_VER = 1.02.a
 PARAMETER HW_INSTANCE = mb_opb
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = debug_module
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = dlmb_cntlr
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = ilmb_cntlr
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.00.b
  PARAMETER HW_INSTANCE = RS232
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = LEDs
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = Push_Button_SW4
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = DIP_Switches
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = ddr
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = DDR_SDRAM_16Mx16
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = tmrctr
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = opb_timer_1
END

BEGIN DRIVER
  PARAMETER DRIVER_NAME = intc
 PARAMETER DRIVER_VER = 1.00.c
 PARAMETER HW_INSTANCE = opb_intc_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = dcm_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = dcm_1
END
___________________________
microblaze-uclinux mailing list
microblaze-uclinux@itee.uq.edu.au
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
Prev by Date: Re: [microblaze-uclinux] Booting uClinux
Next by Date: Re: [microblaze-uclinux] Booting uClinux
Previous by thread: [microblaze-uclinux] Error on lib generation
Next by thread: RE: [microblaze-uclinux] Problem downloading kernel
Index(es):
- Date
- Thread