[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [microblaze-uclinux] Booting uClinux

Hi,
When I download the image.elf instead of the image.bin, I get this:
XMD command: dow image.elf

Terminal Output:
..
..
Freeing init memory: 32K
<0>Kernel panic: No init found.  Try passing init= option to k
ernel.

So there is some difference between downloading the image.bin and image.elf. Anyone have any ideas on that?

John McGrath wrote:
Hi John,
They are attached.
Ive done the steps youve asked.
I think the real problem is that the romfs seems to want to map to memory space 0x00000000-0x000b2000, when my ram is located at 0x81800000. perhaps it cannot find any files in my fs , and that is why it hangs?
Is there a way to test the romfs readability, some code I can enter into the inti sequence perhaps??
My boot log is below.

Cheers,
Note: I only have a small amount of on-chip BRAM memory, and no flash.


Linux version 2.4.29-uc0 (jmcgrath@xcklinux3) (gcc version 2.95.3-4 Xilinx EDK 6
.3 Build EDK_Gmm.12.2) #13 Sat Apr 9 17:31:55 IST 2005
On node 0 totalpages: 2048
zone(0): 2048 pages.
zone(1): 0 pages.
zone(2): 0 pages.
CPU: MICROBLAZE
Console: xmbserial on UARTLite
Kernel command line: °
Calibrating delay loop... 1.93 BogoMIPS
Memory: 8MB = 8MB total
Memory: 6592KB available (595K code, 904K data, 32K init)
Dentry cache hash table entries: 1024 (order: 1, 8192 bytes)
Inode cache hash table entries: 512 (order: 0, 4096 bytes)
Mount cache hash table entries: 512 (order: 0, 4096 bytes)
Buffer cache hash table entries: 1024 (order: 0, 4096 bytes)
Page-cache hash table entries: 2048 (order: 1, 8192 bytes)
POSIX conformance testing by UNIFIX
Linux NET4.0 for Linux 2.4
Based upon Swansea University Computer Society NET3.039
Microblaze UARTlite serial driver version 1.00
ttyS0 at 0xa0000000 (irq = 1) is a Microblaze UARTlite
Starting kswapd
xgpio #0 at 0x81020000 mapped to 0x81020000
Xilinx GPIO registered
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
MBVanilla flash probe(0xff000000,8388608,4): 800000 at ff000000
CFI: Found no Flash device at location zero
Search for id:(00 00) interleave(2) type(2)
Search for id:(00 00) interleave(2) type(2)
Search for id:(00 00) interleave(2) type(2)
Search for id:(00 00) interleave(2) type(1)
Search for id:(00 00) interleave(2) type(1)
Search for id:(00 00) interleave(2) type(1)
Search for id:(00 00) interleave(4) type(2)
Search for id:(00 00) interleave(4) type(2)
Search for id:(00 00) interleave(4) type(2)
Search for id:(00 00) interleave(4) type(1)
Search for id:(00 00) interleave(4) type(1)
Search for id:(00 00) interleave(4) type(1)
JEDEC: Found no Flash device at location zero
MBVanilla ram probe(0x818c58fc,729088,4): b2000 at 818c58fc
Creating 1 MTD partitions on "RAM":
0x00000000-0x000b2000 : "Romfs"
VFS: Mounted root (romfs filesystem) readonly.
jFreeing init memory: 32K

John Williams wrote:

Hi John

John McGrath wrote:

My interrupt order is as follows:

PORT Intr = mdm_intr & uart_intr & timer_intr

I guess this makes the timer interrupt the first one. The order I have here is taken from the ml401 reference design, with the unused peripherals stripped out. My question is, how does uClinux get told of this order? Is there some file I have to manually edit to say which interrupts go where?


This is a red herring.  auto-config automagically handles the IRQ order, and it is not necessary for the timer to be at IRQ0 anyway.

However, you must make sure that you are either copying the auto-config.in file to the right place, or have correctly set your "TARGET_DIR" parameter in the MSS file, so that the MLD/TCL will doing it automatically.

Also, after the auto-config.in changes, you must run "make oldconfig" from uClinux-dist to make sure the changes are picked up.

If you post your MHS/MSS files I'll try to look at it next week.

Cheers,

John

___________________________
microblaze-uclinux mailing list
microblaze-uclinux@itee.uq.edu.au
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/ 





 PARAMETER VERSION = 2.2.0


# BEGIN OS
# PARAMETER OS_NAME = standalone
# PARAMETER OS_VER = 1.00.a
# PARAMETER PROC_INSTANCE = microblaze_0
# PARAMETER STDIN = RS232
# PARAMETER STDOUT = RS232
# END
BEGIN OS
 PARAMETER OS_NAME = uclinux
 PARAMETER OS_VER = 1.00.a
 PARAMETER PROC_INSTANCE = microblaze_0
 PARAMETER stdin = console_uart
 PARAMETER stdout = console_uart
 PARAMETER main_memory = SDRAM_8Mx32
# PARAMETER main_memory_bank = 0
# PARAMETER main_memory_size = 0x4000000
 PARAMETER flash_memory = none
# PARAMETER flash_memory_bank = 1
 PARAMETER lmb_memory = lmb_bram_if_cntlr_0
 PARAMETER target_dir = /home/jmcgrath/projects/uClinux/CVS_dl/Try2b/uClinux-dist/linux-2.4.x/arch/microblaze/platform/uclinux-auto
END


# override the peripheral type of the USB_EMC
# PARAMETER periph_type_overrides = {opb_emc_usb_0 opb_cypress_usb}
BEGIN PROCESSOR
 PARAMETER DRIVER_NAME = cpu
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = microblaze_0
 PARAMETER COMPILER = mb-gcc
 PARAMETER ARCHIVER = mb-ar
# PARAMETER XMDSTUB_PERIPHERAL = debug_module
 PARAMETER CORE_CLOCK_FREQ_HZ = 50000000
END


# BEGIN DRIVER
# PARAMETER DRIVER_NAME = opbarb
# PARAMETER DRIVER_VER = 1.02.a
# PARAMETER HW_INSTANCE = mb_opb
# END
# BEGIN DRIVER
# PARAMETER DRIVER_NAME = uartlite
# PARAMETER DRIVER_VER = 1.00.b
# PARAMETER HW_INSTANCE = debug_module
# END
BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = opb_mdm_0
END

# BEGIN DRIVER
# PARAMETER DRIVER_NAME = bram
# PARAMETER DRIVER_VER = 1.00.a
# PARAMETER HW_INSTANCE = dlmb_cntlr
# END
# BEGIN DRIVER
# PARAMETER DRIVER_NAME = bram
# pwd
# PARAMETER DRIVER_VER = 1.00.a
# PARAMETER HW_INSTANCE = ilmb_cntlr
# END
BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = lmb_bram_if_cntlr_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = lmb_bram_if_cntlr_1
END

# BEGIN DRIVER
# PARAMETER DRIVER_NAME = uartlite
# PARAMETER DRIVER_VER = 1.00.b
# PARAMETER HW_INSTANCE = RS232
# END
BEGIN DRIVER
 PARAMETER HW_INSTANCE = console_uart
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.00.b
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = LEDs_8Bit
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = sdram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = SDRAM_8Mx32
END

# new blocks added
BEGIN DRIVER
 PARAMETER DRIVER_NAME = tmrctr
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = opb_timer_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = intc
 PARAMETER DRIVER_VER = 1.00.c
 PARAMETER HW_INSTANCE = opb_intc_0
END


  

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 6.3 Build EDK_Gmm.11.2
# Mon Mar 21 21:41:48 2005
# Target Board:  Xilinx AFX Virtex-II Pro fg456 Proto Board Rev C
# Family:	 virtex2p
# Device:	 XC2VP7
# Package:	 FG456
# Speed Grade:	 -6
# Processor: Microblaze
# System clock frequency: 50.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory :   8 KB
# Total Off Chip Memory :   8 MB
# - SDRAM_8Mx32 =   8 MB
# ##############################################################################


 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = INPUT
 PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = OUTPUT
 PORT fpga_0_RS232_req_to_send_pin = net_gnd, DIR = OUTPUT
 PORT fpga_0_LEDs_8Bit_GPIO_d_out_pin = fpga_0_LEDs_8Bit_GPIO_d_out, VEC = [0:7], DIR = OUTPUT
 PORT fpga_0_SDRAM_8Mx32_SDRAM_DQ_pin = fpga_0_SDRAM_8Mx32_SDRAM_DQ, VEC = [0:31], DIR = INOUT
 PORT fpga_0_SDRAM_8Mx32_SDRAM_Addr_pin = fpga_0_SDRAM_8Mx32_SDRAM_Addr, VEC = [0:10], DIR = OUTPUT
 PORT fpga_0_SDRAM_8Mx32_SDRAM_DQM_pin = fpga_0_SDRAM_8Mx32_SDRAM_DQM, VEC = [0:3], DIR = OUTPUT
 PORT fpga_0_SDRAM_8Mx32_SDRAM_WEn_pin = fpga_0_SDRAM_8Mx32_SDRAM_WEn, DIR = OUTPUT
 PORT fpga_0_SDRAM_8Mx32_SDRAM_CKE_pin = fpga_0_SDRAM_8Mx32_SDRAM_CKE, DIR = OUTPUT
 PORT fpga_0_SDRAM_8Mx32_SDRAM_CASn_pin = fpga_0_SDRAM_8Mx32_SDRAM_CASn, DIR = OUTPUT
 PORT fpga_0_SDRAM_8Mx32_SDRAM_RASn_pin = fpga_0_SDRAM_8Mx32_SDRAM_RASn, DIR = OUTPUT
 PORT sys_clk_pin = sys_clk_s, DIR = INPUT, SIGIS = CLK
 PORT sys_rst_pin = sys_rst_s, DIR = INPUT


# BEGIN microblaze
# PARAMETER INSTANCE = microblaze_0
# PARAMETER HW_VER = 3.00.a
# PARAMETER C_DEBUG_ENABLED = 1
# PARAMETER C_NUMBER_OF_PC_BRK = 2
# PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
# PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
# BUS_INTERFACE DOPB = mb_opb
# BUS_INTERFACE IOPB = mb_opb
# BUS_INTERFACE DLMB = dlmb
# BUS_INTERFACE ILMB = ilmb
# PORT CLK = sys_clk_s
# PORT DBG_CAPTURE = DBG_CAPTURE_s
# PORT DBG_CLK = DBG_CLK_s
# PORT DBG_REG_EN = DBG_REG_EN_s
# PORT DBG_TDI = DBG_TDI_s
# PORT DBG_TDO = DBG_TDO_s
# PORT DBG_UPDATE = DBG_UPDATE_s
# END
BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_DIV = 1
 PARAMETER C_USE_MSR_INSTR = 1
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
# PARAMETER C_UNALIGNED_EXCEPTIONS = 1
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_ICACHE_BASEADDR = 0x10000000
 PARAMETER C_ICACHE_HIGHADDR = 0x13FFFFFF
 PARAMETER C_CACHE_BYTE_SIZE = 16384
 PARAMETER C_ADDR_TAG_BITS = 11
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_DCACHE_BASEADDR = 0x10000000
 PARAMETER C_DCACHE_HIGHADDR = 0x13FFFFFF
 PARAMETER C_DCACHE_BYTE_SIZE = 16384
 PARAMETER C_DCACHE_ADDR_TAG = 11
 PARAMETER C_FSL_LINKS = 1
 BUS_INTERFACE SFSL0 = download_link
 BUS_INTERFACE DLMB = lmb_v10_1
 BUS_INTERFACE ILMB = lmb_v10_0
 BUS_INTERFACE DOPB = opb_v20_0
 BUS_INTERFACE IOPB = opb_v20_0
 PORT CLK = sys_clk_s
 PORT Interrupt = ext_irq
END

# Support for OPB_IBA chipscope core
# stop MB when ChipScope triggers
# PORT DBG_STOP = mb_stop
# Trigger Chipscope if MB is halted (by xmd/gdb etc)
# PORT MB_Halted = mb_halt_trig
BEGIN opb_v20
 PARAMETER INSTANCE = opb_v20_0
 PARAMETER HW_VER = 1.10.b
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT OPB_Clk = sys_clk_s
END

# BEGIN opb_mdm
# PARAMETER INSTANCE = debug_module
# PARAMETER HW_VER = 2.00.a
# PARAMETER C_MB_DBG_PORTS = 1
# PARAMETER C_USE_UART = 1
# PARAMETER C_UART_WIDTH = 8
# PARAMETER C_BASEADDR = 0x81000000
# PARAMETER C_HIGHADDR = 0x8100ffff
# BUS_INTERFACE SOPB = mb_opb
# PORT OPB_Clk = sys_clk_s
# PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
# PORT DBG_CLK_0 = DBG_CLK_s
# PORT DBG_REG_EN_0 = DBG_REG_EN_s
# PORT DBG_TDI_0 = DBG_TDI_s
# PORT DBG_TDO_0 = DBG_TDO_s
# PORT DBG_UPDATE_0 = DBG_UPDATE_s
# END
BEGIN opb_mdm
 PARAMETER INSTANCE = opb_mdm_0
 PARAMETER HW_VER = 2.01.a
 PARAMETER C_BASEADDR = 0xfffe8000
 PARAMETER C_HIGHADDR = 0xfffe80ff
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_WRITE_FSL_PORTS = 1
 BUS_INTERFACE SOPB = opb_v20_0
 BUS_INTERFACE MFSL0 = download_link
 PORT Interrupt = mdm_intr
END

BEGIN lmb_v10
 PARAMETER INSTANCE = lmb_v10_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = lmb_v10_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

# BEGIN lmb_bram_if_cntlr
# PARAMETER INSTANCE = dlmb_cntlr
# PARAMETER HW_VER = 1.00.b
# PARAMETER C_BASEADDR = 0x00000000
# PARAMETER C_HIGHADDR = 0x00001fff
# BUS_INTERFACE SLMB = dlmb
# BUS_INTERFACE BRAM_PORT = dlmb_port
# END
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = lmb_bram_if_cntlr_0
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x0000_0000
 PARAMETER C_HIGHADDR = 0x0000_1fff
 BUS_INTERFACE SLMB = lmb_v10_1
 BUS_INTERFACE BRAM_PORT = conn_0
END

# BEGIN lmb_bram_if_cntlr
# PARAMETER INSTANCE = ilmb_cntlr
# PARAMETER HW_VER = 1.00.b
# PARAMETER C_BASEADDR = 0x00000000
# PARAMETER C_HIGHADDR = 0x00001fff
# BUS_INTERFACE SLMB = ilmb
# BUS_INTERFACE BRAM_PORT = ilmb_port
# END
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = lmb_bram_if_cntlr_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x0000_0000
 PARAMETER C_HIGHADDR = 0x0000_1fff
 BUS_INTERFACE SLMB = lmb_v10_0
 BUS_INTERFACE BRAM_PORT = conn_1
END

# BEGIN bram_block
# PARAMETER INSTANCE = lmb_bram
# PARAMETER HW_VER = 1.00.a
# BUS_INTERFACE PORTA = ilmb_port
# BUS_INTERFACE PORTB = dlmb_port
# END
BEGIN bram_block
 PARAMETER INSTANCE = bram_block_0
 PARAMETER HW_VER = 1.00.a
 #PARAMETER C_MEMSIZE = 8192
 #PARAMETER C_PORT_DWIDTH = 32
 #PARAMETER C_PORT_AWIDTH = 13
 #PARAMETER C_NUM_WE = 4
 BUS_INTERFACE PORTA = conn_0
 BUS_INTERFACE PORTB = conn_1
END

# BEGIN opb_uartlite
# PARAMETER INSTANCE = RS232
# PARAMETER HW_VER = 1.00.b
# PARAMETER C_BAUDRATE = 9600
# PARAMETER C_DATA_BITS = 8
# PARAMETER C_ODD_PARITY = 0
# PARAMETER C_USE_PARITY = 0
# PARAMETER C_CLK_FREQ = 50000000
# PARAMETER C_BASEADDR = 0x81010000
# PARAMETER C_HIGHADDR = 0x8101ffff
# BUS_INTERFACE SOPB = mb_opb
# PORT OPB_Clk = sys_clk_s
# PORT RX = fpga_0_RS232_RX
# PORT TX = fpga_0_RS232_TX
# END
BEGIN opb_uartlite
 PARAMETER INSTANCE = console_uart
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
# PARAMETER C_CLK_FREQ = 100_000_000
# PARAMETER C_CLK_FREQ = 66_666_667
 PARAMETER C_CLK_FREQ = 50_000_000
 PARAMETER C_BASEADDR = 0xa0000000
 PARAMETER C_HIGHADDR = 0xa0001fff
 BUS_INTERFACE SOPB = opb_v20_0
 PORT Interrupt = uart_intr
 PORT OPB_Clk = sys_clk_s
 PORT RX = fpga_0_RS232_RX
 PORT TX = fpga_0_RS232_TX
END

BEGIN opb_gpio
 PARAMETER INSTANCE = LEDs_8Bit
 PARAMETER HW_VER = 3.01.a
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x81020000
 PARAMETER C_HIGHADDR = 0x8102ffff
 BUS_INTERFACE SOPB = opb_v20_0
 PORT OPB_Clk = sys_clk_s
 PORT GPIO_d_out = fpga_0_LEDs_8Bit_GPIO_d_out
END

BEGIN opb_sdram
 PARAMETER INSTANCE = SDRAM_8Mx32
 PARAMETER HW_VER = 1.00.e
 PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 1
 PARAMETER C_OPB_CLK_PERIOD_PS = 20000
 PARAMETER C_SDRAM_TCCD = 1
 PARAMETER C_SDRAM_TRAS = 50000
 PARAMETER C_SDRAM_TRC = 100000
 PARAMETER C_SDRAM_TRFC = 100000
 PARAMETER C_SDRAM_TRCD = 20000
 PARAMETER C_SDRAM_TRRD = 20000
 PARAMETER C_SDRAM_TRP = 20000
 PARAMETER C_SDRAM_TREF = 64
 PARAMETER C_SDRAM_CAS_LAT = 2
 PARAMETER C_SDRAM_COL_AWIDTH = 8
 PARAMETER C_SDRAM_BANK_AWIDTH = 2
 PARAMETER C_SDRAM_AWIDTH = 11
 PARAMETER C_SDRAM_DWIDTH = 32
 PARAMETER C_BASEADDR = 0x81800000
 PARAMETER C_HIGHADDR = 0x81ffffff
 BUS_INTERFACE SOPB = opb_v20_0
 PORT OPB_Clk = sys_clk_s
 PORT SDRAM_CLK_in = sys_clk_s
 PORT SDRAM_DQ = fpga_0_SDRAM_8Mx32_SDRAM_DQ
 PORT SDRAM_Addr = fpga_0_SDRAM_8Mx32_SDRAM_Addr
 PORT SDRAM_DQM = fpga_0_SDRAM_8Mx32_SDRAM_DQM
 PORT SDRAM_WEn = fpga_0_SDRAM_8Mx32_SDRAM_WEn
 PORT SDRAM_CKE = fpga_0_SDRAM_8Mx32_SDRAM_CKE
 PORT SDRAM_CASn = fpga_0_SDRAM_8Mx32_SDRAM_CASn
 PORT SDRAM_RASn = fpga_0_SDRAM_8Mx32_SDRAM_RASn
END

# add new stuff not in the defualt project
BEGIN fsl_v20
 PARAMETER INSTANCE = download_link
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT FSL_Clk = sys_clk_s
END

BEGIN opb_intc
 PARAMETER INSTANCE = opb_intc_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_BASEADDR = 0xD1000FC0
 PARAMETER C_HIGHADDR = 0xD1000FDF
 BUS_INTERFACE SOPB = opb_v20_0
 PORT OPB_Clk = sys_clk_s
 PORT Intr = mdm_intr & uart_intr & timer_intr
 PORT Irq = ext_irq
END

BEGIN opb_timer
 PARAMETER INSTANCE = opb_timer_0
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 0
 PARAMETER C_BASEADDR = 0xa2000000
 PARAMETER C_HIGHADDR = 0xa20000ff
 BUS_INTERFACE SOPB = opb_v20_0
 PORT OPB_Clk = sys_clk_s
 PORT Interrupt = timer_intr
END