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Hi Brett, Thanks for the offer to help! My MHS and MSS are pretty simple (attached) and I also attached the auto-config.in. The version of the kernel was downloaded completly new wednesday of this week. the only previous kernel I tried was late feb/start of march, and I had the same problem as I'm having now... I have a pretty simple system - no caches enabled, etc. I assume that somehow auto-confing.in knows what parameters to pass to gcc to enable/disable certain processor features? One thing about the mdm - the version of it I am using is the version that John Williams had in his ml401 reference platform, i.e. 2.01.a Maybe If I could get a look at your MHS/MSS I could try put your settings into my baord? (I guess it's just a ucf change needed, all else should be ok!) What version of the EDK are you using? Cheers, John mcnernbm@notes.udayton.edu wrote:
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# ############################################################################## # Created by Base System Builder Wizard for Xilinx EDK 6.3 Build EDK_Gmm.11.2 # Mon Mar 21 21:41:48 2005 # Target Board: Xilinx AFX Virtex-II Pro fg456 Proto Board Rev C # Family: virtex2p # Device: XC2VP7 # Package: FG456 # Speed Grade: -6 # Processor: Microblaze # System clock frequency: 50.000000 MHz # Debug interface: On-Chip HW Debug Module # On Chip Memory : 8 KB # Total Off Chip Memory : 8 MB # - SDRAM_8Mx32 = 8 MB # ############################################################################## PARAMETER VERSION = 2.1.0 PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = INPUT PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = OUTPUT PORT fpga_0_RS232_req_to_send_pin = net_gnd, DIR = OUTPUT PORT fpga_0_LEDs_8Bit_GPIO_d_out_pin = fpga_0_LEDs_8Bit_GPIO_d_out, VEC = [0:7], DIR = OUTPUT PORT fpga_0_SDRAM_8Mx32_SDRAM_DQ_pin = fpga_0_SDRAM_8Mx32_SDRAM_DQ, VEC = [0:31], DIR = INOUT PORT fpga_0_SDRAM_8Mx32_SDRAM_Addr_pin = fpga_0_SDRAM_8Mx32_SDRAM_Addr, VEC = [0:10], DIR = OUTPUT PORT fpga_0_SDRAM_8Mx32_SDRAM_DQM_pin = fpga_0_SDRAM_8Mx32_SDRAM_DQM, VEC = [0:3], DIR = OUTPUT PORT fpga_0_SDRAM_8Mx32_SDRAM_WEn_pin = fpga_0_SDRAM_8Mx32_SDRAM_WEn, DIR = OUTPUT PORT fpga_0_SDRAM_8Mx32_SDRAM_CKE_pin = fpga_0_SDRAM_8Mx32_SDRAM_CKE, DIR = OUTPUT PORT fpga_0_SDRAM_8Mx32_SDRAM_CASn_pin = fpga_0_SDRAM_8Mx32_SDRAM_CASn, DIR = OUTPUT PORT fpga_0_SDRAM_8Mx32_SDRAM_RASn_pin = fpga_0_SDRAM_8Mx32_SDRAM_RASn, DIR = OUTPUT PORT sys_clk_pin = sys_clk_s, DIR = INPUT, SIGIS = CLK PORT sys_rst_pin = sys_rst_s, DIR = INPUT BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER HW_VER = 3.00.a PARAMETER C_USE_BARREL = 1 PARAMETER C_USE_DIV = 1 PARAMETER C_USE_MSR_INSTR = 1 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_NUMBER_OF_PC_BRK = 2 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1 PARAMETER C_FSL_LINKS = 1 BUS_INTERFACE SFSL0 = download_link BUS_INTERFACE DLMB = lmb_v10_1 BUS_INTERFACE ILMB = lmb_v10_0 BUS_INTERFACE DOPB = opb_v20_0 BUS_INTERFACE IOPB = opb_v20_0 PORT CLK = sys_clk_s PORT Interrupt = ext_irq END BEGIN opb_v20 PARAMETER INSTANCE = opb_v20_0 PARAMETER HW_VER = 1.10.b PARAMETER C_EXT_RESET_HIGH = 0 PORT SYS_Rst = sys_rst_s PORT OPB_Clk = sys_clk_s END BEGIN opb_mdm PARAMETER INSTANCE = opb_mdm_0 PARAMETER HW_VER = 2.01.a PARAMETER C_BASEADDR = 0xfffe8000 PARAMETER C_HIGHADDR = 0xfffe80ff PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER C_WRITE_FSL_PORTS = 1 BUS_INTERFACE SOPB = opb_v20_0 BUS_INTERFACE MFSL0 = download_link PORT Interrupt = mdm_intr END BEGIN lmb_v10 PARAMETER INSTANCE = lmb_v10_1 PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT SYS_Rst = sys_rst_s PORT LMB_Clk = sys_clk_s END BEGIN lmb_v10 PARAMETER INSTANCE = lmb_v10_0 PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT SYS_Rst = sys_rst_s PORT LMB_Clk = sys_clk_s END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = lmb_bram_if_cntlr_0 PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x0000_0000 PARAMETER C_HIGHADDR = 0x0000_7fff BUS_INTERFACE SLMB = lmb_v10_1 BUS_INTERFACE BRAM_PORT = conn_0 END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = lmb_bram_if_cntlr_1 PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x0000_0000 PARAMETER C_HIGHADDR = 0x0000_7fff BUS_INTERFACE SLMB = lmb_v10_0 BUS_INTERFACE BRAM_PORT = conn_1 END BEGIN bram_block PARAMETER INSTANCE = bram_block_0 PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = conn_0 BUS_INTERFACE PORTB = conn_1 END BEGIN opb_uartlite PARAMETER INSTANCE = console_uart PARAMETER HW_VER = 1.00.b PARAMETER C_BAUDRATE = 115200 PARAMETER C_DATA_BITS = 8 PARAMETER C_USE_PARITY = 0 PARAMETER C_ODD_PARITY = 0 PARAMETER C_CLK_FREQ = 50_000_000 PARAMETER C_BASEADDR = 0xa0000000 PARAMETER C_HIGHADDR = 0xa0001fff BUS_INTERFACE SOPB = opb_v20_0 PORT Interrupt = uart_intr PORT OPB_Clk = sys_clk_s PORT RX = fpga_0_RS232_RX PORT TX = fpga_0_RS232_TX END BEGIN opb_gpio PARAMETER INSTANCE = LEDs_8Bit PARAMETER HW_VER = 3.01.a PARAMETER C_GPIO_WIDTH = 8 PARAMETER C_IS_DUAL = 0 PARAMETER C_IS_BIDIR = 0 PARAMETER C_ALL_INPUTS = 0 PARAMETER C_BASEADDR = 0x81020000 PARAMETER C_HIGHADDR = 0x8102ffff BUS_INTERFACE SOPB = opb_v20_0 PORT OPB_Clk = sys_clk_s PORT GPIO_d_out = fpga_0_LEDs_8Bit_GPIO_d_out END BEGIN opb_sdram PARAMETER INSTANCE = SDRAM_8Mx32 PARAMETER HW_VER = 1.00.e PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 1 PARAMETER C_OPB_CLK_PERIOD_PS = 20000 PARAMETER C_SDRAM_TCCD = 1 PARAMETER C_SDRAM_TRAS = 50000 PARAMETER C_SDRAM_TRC = 100000 PARAMETER C_SDRAM_TRFC = 100000 PARAMETER C_SDRAM_TRCD = 20000 PARAMETER C_SDRAM_TRRD = 20000 PARAMETER C_SDRAM_TRP = 20000 PARAMETER C_SDRAM_TREF = 64 PARAMETER C_SDRAM_CAS_LAT = 2 PARAMETER C_SDRAM_COL_AWIDTH = 8 PARAMETER C_SDRAM_BANK_AWIDTH = 2 PARAMETER C_SDRAM_AWIDTH = 11 PARAMETER C_SDRAM_DWIDTH = 32 PARAMETER C_BASEADDR = 0x81800000 PARAMETER C_HIGHADDR = 0x81ffffff BUS_INTERFACE SOPB = opb_v20_0 PORT OPB_Clk = sys_clk_s PORT SDRAM_CLK_in = sys_clk_s PORT SDRAM_DQ = fpga_0_SDRAM_8Mx32_SDRAM_DQ PORT SDRAM_Addr = fpga_0_SDRAM_8Mx32_SDRAM_Addr PORT SDRAM_DQM = fpga_0_SDRAM_8Mx32_SDRAM_DQM PORT SDRAM_WEn = fpga_0_SDRAM_8Mx32_SDRAM_WEn PORT SDRAM_CKE = fpga_0_SDRAM_8Mx32_SDRAM_CKE PORT SDRAM_CASn = fpga_0_SDRAM_8Mx32_SDRAM_CASn PORT SDRAM_RASn = fpga_0_SDRAM_8Mx32_SDRAM_RASn END # add new stuff not in the defualt project BEGIN fsl_v20 PARAMETER INSTANCE = download_link PARAMETER HW_VER = 2.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT SYS_Rst = sys_rst_s PORT FSL_Clk = sys_clk_s END BEGIN opb_intc PARAMETER INSTANCE = opb_intc_0 PARAMETER HW_VER = 1.00.c PARAMETER C_BASEADDR = 0xD1000FC0 PARAMETER C_HIGHADDR = 0xD1000FDF BUS_INTERFACE SOPB = opb_v20_0 PORT OPB_Clk = sys_clk_s PORT Intr = mdm_intr & uart_intr & timer_intr PORT Irq = ext_irq END BEGIN opb_timer PARAMETER INSTANCE = opb_timer_0 PARAMETER HW_VER = 1.00.b PARAMETER C_COUNT_WIDTH = 32 PARAMETER C_ONE_TIMER_ONLY = 0 PARAMETER C_BASEADDR = 0xa2000000 PARAMETER C_HIGHADDR = 0xa20000ff BUS_INTERFACE SOPB = opb_v20_0 PORT OPB_Clk = sys_clk_s PORT Interrupt = timer_intr END
PARAMETER VERSION = 2.2.0
BEGIN OS
PARAMETER OS_NAME = uclinux
PARAMETER OS_VER = 1.00.a
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER stdin = console_uart
PARAMETER stdout = console_uart
PARAMETER main_memory = SDRAM_8Mx32
PARAMETER flash_memory = none
PARAMETER lmb_memory = lmb_bram_if_cntlr_0
PARAMETER target_dir = /home/jmcgrath/projects/uClinux/CVS_dl/Try_2104/uClinux-dist/linux-2.4.x/arch/microblaze/platform/uclinux-auto
END
# override the peripheral type of the USB_EMC
# PARAMETER periph_type_overrides = {opb_emc_usb_0 opb_cypress_usb}
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = microblaze_0
PARAMETER COMPILER = mb-gcc
PARAMETER ARCHIVER = mb-ar
PARAMETER CORE_CLOCK_FREQ_HZ = 50000000
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = opb_mdm_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = lmb_bram_if_cntlr_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = lmb_bram_if_cntlr_1
END
BEGIN DRIVER
PARAMETER HW_INSTANCE = console_uart
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.00.b
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 2.00.a
PARAMETER HW_INSTANCE = LEDs_8Bit
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = sdram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = SDRAM_8Mx32
END
# new blocks added
BEGIN DRIVER
PARAMETER DRIVER_NAME = tmrctr
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = opb_timer_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = intc
PARAMETER DRIVER_VER = 1.00.c
PARAMETER HW_INSTANCE = opb_intc_0
END
############################################################ # # CAUTION: This file is automatically generated by libgen. # Version: Xilinx EDK 6.3 EDK_Gmm.12.3 # Description: uClinux Configuration File # ############################################################ # MAIN_MEMORY Settings define_hex CONFIG_XILINX_ERAM_START 0x81800000 define_hex CONFIG_XILINX_ERAM_SIZE 0x00800000 # LMB_MEMORY Settings define_hex CONFIG_XILINX_LMB_START 0x00000000 define_hex CONFIG_XILINX_LMB_SIZE 0x00008000 # System Clock Frequency define_int CONFIG_XILINX_CPU_CLOCK_FREQ 50000000 # Definitions for MICROBLAZE0 define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0 define_string CONFIG_XILINX_MICROBLAZE0_FAMILY virtex2p define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0 define_int CONFIG_XILINX_MICROBLAZE0_D_OPB 1 define_int CONFIG_XILINX_MICROBLAZE0_D_LMB 1 define_int CONFIG_XILINX_MICROBLAZE0_I_OPB 1 define_int CONFIG_XILINX_MICROBLAZE0_I_LMB 1 define_int CONFIG_XILINX_MICROBLAZE0_USE_BARREL 1 define_int CONFIG_XILINX_MICROBLAZE0_USE_DIV 1 define_int CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR 1 define_int CONFIG_XILINX_MICROBLAZE0_UNALIGNED_EXCEPTIONS 0 define_int CONFIG_XILINX_MICROBLAZE0_ILL_OPCODE_EXCEPTION 0 define_int CONFIG_XILINX_MICROBLAZE0_IOPB_BUS_EXCEPTION 0 define_int CONFIG_XILINX_MICROBLAZE0_DOPB_BUS_EXCEPTION 0 define_int CONFIG_XILINX_MICROBLAZE0_DIV_ZERO_EXCEPTION 0 define_int CONFIG_XILINX_MICROBLAZE0_DEBUG_ENABLED 1 define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_PBRK 2 define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK 1 define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK 1 define_int CONFIG_XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE 0 define_int CONFIG_XILINX_MICROBLAZE0_EDGE_IS_POSITIVE 1 define_int CONFIG_XILINX_MICROBLAZE0_FSL_LINKS 1 define_int CONFIG_XILINX_MICROBLAZE0_FSL_DATA_SIZE 32 define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR 0x00000000 define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR 0x3FFFFFFF define_int CONFIG_XILINX_MICROBLAZE0_USE_ICACHE 0 define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_ICACHE_WR 1 define_int CONFIG_XILINX_MICROBLAZE0_ADDR_TAG_BITS 17 define_int CONFIG_XILINX_MICROBLAZE0_CACHE_BYTE_SIZE 8192 define_int CONFIG_XILINX_MICROBLAZE0_ICACHE_USE_FSL 0 define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR 0x00000000 define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR 0x3FFFFFFF define_int CONFIG_XILINX_MICROBLAZE0_USE_DCACHE 0 define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_DCACHE_WR 1 define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_ADDR_TAG 17 define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE 8192 define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_USE_FSL 0 define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0 define_string CONFIG_XILINX_MICROBLAZE0_HW_VER 3.00.a # Definitions for LMB_BRAM_IF_CNTLR_0 define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE lmb_bram_if_cntlr_0 define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR 0x00000000 define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR 0x00007FFF define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_MASK 0x21000000 define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH 32 define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH 32 define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE lmb_bram_if_cntlr_0 define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER 1.00.b # Definitions for LMB_BRAM_IF_CNTLR_1 define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE lmb_bram_if_cntlr_1 define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR 0x00000000 define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR 0x00007FFF define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_MASK 0x21000000 define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH 32 define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH 32 define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE lmb_bram_if_cntlr_1 define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER 1.00.b # Definitions for MDM_0 define_string CONFIG_XILINX_MDM_0_INSTANCE opb_mdm_0 define_hex CONFIG_XILINX_MDM_0_BASEADDR 0xFFFE8000 define_hex CONFIG_XILINX_MDM_0_HIGHADDR 0xFFFE80FF define_int CONFIG_XILINX_MDM_0_OPB_DWIDTH 32 define_int CONFIG_XILINX_MDM_0_OPB_AWIDTH 32 define_string CONFIG_XILINX_MDM_0_FAMILY virtex2p define_int CONFIG_XILINX_MDM_0_MB_DBG_PORTS 1 define_int CONFIG_XILINX_MDM_0_USE_UART 1 define_int CONFIG_XILINX_MDM_0_UART_WIDTH 8 define_int CONFIG_XILINX_MDM_0_WRITE_FSL_PORTS 1 define_string CONFIG_XILINX_MDM_0_INSTANCE opb_mdm_0 define_string CONFIG_XILINX_MDM_0_HW_VER 2.01.a define_int CONFIG_XILINX_MDM_0_IRQ 2 # Definitions for UARTLITE_0 define_string CONFIG_XILINX_UARTLITE_0_INSTANCE console_uart define_hex CONFIG_XILINX_UARTLITE_0_BASEADDR 0xA0000000 define_hex CONFIG_XILINX_UARTLITE_0_HIGHADDR 0xA0001FFF define_int CONFIG_XILINX_UARTLITE_0_OPB_DWIDTH 32 define_int CONFIG_XILINX_UARTLITE_0_OPB_AWIDTH 32 define_int CONFIG_XILINX_UARTLITE_0_DATA_BITS 8 define_int CONFIG_XILINX_UARTLITE_0_CLK_FREQ 50000000 define_int CONFIG_XILINX_UARTLITE_0_BAUDRATE 115200 define_int CONFIG_XILINX_UARTLITE_0_USE_PARITY 0 define_int CONFIG_XILINX_UARTLITE_0_ODD_PARITY 0 define_string CONFIG_XILINX_UARTLITE_0_INSTANCE console_uart define_string CONFIG_XILINX_UARTLITE_0_HW_VER 1.00.b define_int CONFIG_XILINX_UARTLITE_0_IRQ 1 # Definitions for GPIO_0 define_string CONFIG_XILINX_GPIO_0_INSTANCE LEDs_8Bit define_hex CONFIG_XILINX_GPIO_0_BASEADDR 0x81020000 define_hex CONFIG_XILINX_GPIO_0_HIGHADDR 0x8102FFFF define_int CONFIG_XILINX_GPIO_0_USER_ID_CODE 3 define_int CONFIG_XILINX_GPIO_0_OPB_AWIDTH 32 define_int CONFIG_XILINX_GPIO_0_OPB_DWIDTH 32 define_string CONFIG_XILINX_GPIO_0_FAMILY virtex2p define_int CONFIG_XILINX_GPIO_0_GPIO_WIDTH 8 define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS 0 define_int CONFIG_XILINX_GPIO_0_INTERRUPT_PRESENT 0 define_int CONFIG_XILINX_GPIO_0_IS_BIDIR 0 define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT 0x00000000 define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT 0xFFFFFFFF define_int CONFIG_XILINX_GPIO_0_IS_DUAL 0 define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS_2 0 define_int CONFIG_XILINX_GPIO_0_IS_BIDIR_2 1 define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT_2 0x00000000 define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT_2 0xFFFFFFFF define_string CONFIG_XILINX_GPIO_0_INSTANCE LEDs_8Bit define_string CONFIG_XILINX_GPIO_0_HW_VER 3.01.a # Definitions for SDRAM_0 define_string CONFIG_XILINX_SDRAM_0_INSTANCE SDRAM_8Mx32 define_int CONFIG_XILINX_SDRAM_0_INCLUDE_BURST_SUPPORT 1 define_int CONFIG_XILINX_SDRAM_0_INCLUDE_HIGHSPEED_PIPE 1 define_int CONFIG_XILINX_SDRAM_0_USE_POSEDGE_OUTREGS 0 define_string CONFIG_XILINX_SDRAM_0_FAMILY virtex2p define_int CONFIG_XILINX_SDRAM_0_SDRAM_TMRD 2 define_int CONFIG_XILINX_SDRAM_0_SDRAM_TWR 15000 define_int CONFIG_XILINX_SDRAM_0_SDRAM_TCCD 1 define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRAS 50000 define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRC 100000 define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRFC 100000 define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRCD 20000 define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRRD 20000 define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRP 20000 define_int CONFIG_XILINX_SDRAM_0_SDRAM_TREF 64 define_int CONFIG_XILINX_SDRAM_0_SDRAM_REFRESH_NUMROWS 8192 define_int CONFIG_XILINX_SDRAM_0_SDRAM_CAS_LAT 2 define_int CONFIG_XILINX_SDRAM_0_SDRAM_DWIDTH 32 define_int CONFIG_XILINX_SDRAM_0_SDRAM_AWIDTH 11 define_int CONFIG_XILINX_SDRAM_0_SDRAM_COL_AWIDTH 8 define_int CONFIG_XILINX_SDRAM_0_SDRAM_BANK_AWIDTH 2 define_int CONFIG_XILINX_SDRAM_0_SDRAM_TREFI 7812500 define_hex CONFIG_XILINX_SDRAM_0_BASEADDR 0x81800000 define_hex CONFIG_XILINX_SDRAM_0_HIGHADDR 0x81FFFFFF define_int CONFIG_XILINX_SDRAM_0_OPB_DWIDTH 32 define_int CONFIG_XILINX_SDRAM_0_OPB_AWIDTH 32 define_int CONFIG_XILINX_SDRAM_0_OPB_CLK_PERIOD_PS 20000 define_int CONFIG_XILINX_SDRAM_0_SIM_INIT_TIME_PS 100000000 define_string CONFIG_XILINX_SDRAM_0_INSTANCE SDRAM_8Mx32 define_string CONFIG_XILINX_SDRAM_0_HW_VER 1.00.e # Definitions for INTC_0 define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0 define_string CONFIG_XILINX_INTC_0_FAMILY virtex2p define_int CONFIG_XILINX_INTC_0_Y 0 define_int CONFIG_XILINX_INTC_0_X 0 define_string CONFIG_XILINX_INTC_0_U_SET intc define_int CONFIG_XILINX_INTC_0_OPB_AWIDTH 32 define_int CONFIG_XILINX_INTC_0_OPB_DWIDTH 32 define_hex CONFIG_XILINX_INTC_0_BASEADDR 0xD1000FC0 define_hex CONFIG_XILINX_INTC_0_HIGHADDR 0xD1000FDF define_int CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS 3 define_hex CONFIG_XILINX_INTC_0_KIND_OF_INTR 0x00000006 define_hex CONFIG_XILINX_INTC_0_KIND_OF_EDGE 0x00000006 define_hex CONFIG_XILINX_INTC_0_KIND_OF_LVL 0x00000001 define_int CONFIG_XILINX_INTC_0_HAS_IPR 1 define_int CONFIG_XILINX_INTC_0_HAS_SIE 1 define_int CONFIG_XILINX_INTC_0_HAS_CIE 1 define_int CONFIG_XILINX_INTC_0_HAS_IVR 1 define_int CONFIG_XILINX_INTC_0_IRQ_IS_LEVEL 1 define_int CONFIG_XILINX_INTC_0_IRQ_ACTIVE 1 define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0 define_string CONFIG_XILINX_INTC_0_HW_VER 1.00.c # Definitions for TIMER_0 define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_0 define_string CONFIG_XILINX_TIMER_0_FAMILY virtex2p define_int CONFIG_XILINX_TIMER_0_COUNT_WIDTH 32 define_int CONFIG_XILINX_TIMER_0_ONE_TIMER_ONLY 0 define_int CONFIG_XILINX_TIMER_0_TRIG0_ASSERT 1 define_int CONFIG_XILINX_TIMER_0_TRIG1_ASSERT 1 define_int CONFIG_XILINX_TIMER_0_GEN0_ASSERT 1 define_int CONFIG_XILINX_TIMER_0_GEN1_ASSERT 1 define_int CONFIG_XILINX_TIMER_0_OPB_AWIDTH 32 define_int CONFIG_XILINX_TIMER_0_OPB_DWIDTH 32 define_hex CONFIG_XILINX_TIMER_0_BASEADDR 0xA2000000 define_hex CONFIG_XILINX_TIMER_0_HIGHADDR 0xA20000FF define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_0 define_string CONFIG_XILINX_TIMER_0_HW_VER 1.00.b define_int CONFIG_XILINX_TIMER_0_IRQ 0 # Peripheral counts define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES 2 define_int CONFIG_XILINX_TIMER_NUM_INSTANCES 1 define_int CONFIG_XILINX_INTC_NUM_INSTANCES 1 define_int CONFIG_XILINX_UARTLITE_NUM_INSTANCES 1 define_int CONFIG_XILINX_MDM_NUM_INSTANCES 1 define_int CONFIG_XILINX_SDRAM_NUM_INSTANCES 1 define_int CONFIG_XILINX_GPIO_NUM_INSTANCES 1