[microblaze-uclinux] microblaze performance

[Rudolf Usselmann <rudi@xxxxxxxx>]

Howdy all !

I was playing around a bit with the cache size and trying to
find a trade off of cache size vs BRAM usage. In my applications,
it seems that I never have enough BRAMs, so I try to justify
very carefully where and how many BRAMs I use.

Here are some of my findings. The tests where performed on a
Virtex II Pro 20, soc running at 66.66 MHz, the first column
is the size of icache/dcache.

16k/16k, 5M dhrystone: 42030.9 dhrystone/sec  (24 extra BRAMs)
 8k/8k,  5M dhrystone: 41830.5 dhrystone/sec  (12 extra BRAMs)
 4k/4k,  5M dhrystone: 41480.0 dhrystone/sec  ( 9 extra BRAMs)
 2k/2k,  5M dhrystone: 19957.7 dhrystone/sec  ( 8 extra BRAMs)
 0k/0k,  5M dhrystone:  4815.4 dhrystone/sec  ( 0 extra BRAMs)

Looks like 4K/4K is a optimum setting. Bogo MIPS stayed pretty
much constant at 32.97 regardless of cache size (which I guess
does make sense).

Anybody else looked in to this before ? Any other finding ?

Regards,
rudi
=============================================================
Rudolf Usselmann,  ASICS World Services,  http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis

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