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Re: [microblaze-uclinux] Device drivers for a Linux kernel with cachesbut no MMU support
Paul Hartke wrote:
>I'm trying to wrap my mind around writing device drivers for a Linux kernel
>with caches but no MMU support. Although Microblaze currently only offers
>write-through caches, coherency with a DMA engine must be enforced by
>invalidating any cache lines that the DMA engine could end up touching.
>This coherency issue is generally bypassed by allocating DMA buffer
>descriptors in non-cachable memory:
>
>drivers/net/xilinx_enet/adapter.c
> /* calc size of descriptor space pool; alloc from non-cached memory
>*/
> dftsize = (XEM_DFT_RECV_DESC + XEM_DFT_SEND_DESC) *
> sizeof (XBufDescriptor);
>
> lp->desc_space = consistent_alloc(GFP_ATOMIC, dftsize,
> &lp->desc_space_handle);
> if (lp->desc_space == 0) {
> return -1;
> }
> lp->desc_space_size = dftsize;
>
>However, how does Microblaze uclinux do this exactly without an MMU? One
>solution is to have Microblaze itself have a chunk of noncached memory and
>put the descriptors there. But, how would the kernel know about this
>memory? In addition, most microblaze designs I've seen cache the whole
>
user can choose the range for cacheable range, you can leave some ram
(sdram) not covered by caheable range at the bottom of your SDRAM
still don't know hoy to let the kernell know about this arangement,
probably you can use some driver init parameters to define the range for
your DMA zone, when you start the driver, or make a pair (or single)
register in your peripheral (if is yours) where you store the range, to
be probed by the driver (sounds more like a hack)
Aurash
>memory space.
>
>The other approach is to invalidate the desciptors every time they are
>passed to the DMA engine but, at least for the case of the Xilinx Ethernet
>drivers, means mucking with them.
>
>How are folks handling this?
>
>Thanks.
>Paul
>
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>
>
>
>
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