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[microblaze-uclinux] Compilation error

To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] Compilation error
From: Anuroop M <anuroop.m@xxxxxxxxx>
Date: Tue, 14 Jun 2005 15:29:45 +0530
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In-reply-to: <42AE3021.5060201@itee.uq.edu.au>
References: <OFCE166768.2EFF64DF-ON8525701F.007C9037-8525701F.007CC8F9@notes.udayton.edu> <42AE3021.5060201@itee.uq.edu.au>
Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxx

Hi all,
          i had generated an auto-config.in for a custom h/w which
contains a console UART and an ethernet on v2p -fg456 board. there is
no flash or ROM present in the h/w .
But wen i compile the kernel with ethernet support enabled, it gives
me an error saying that 'no timer peripheral included' . but i had
included an opb_timer in h/w . still it throws the same error.

can any one help me to come out of this issue...

auto-config.in is attached with this mail ..  plz.. let me know if any
mistake in that..


--Anuroop

############################################################
# 
# CAUTION: This file is automatically generated by libgen.
# Version: Xilinx EDK 6.3 EDK_Gmm.12.3 
# Description: uClinux Configuration File
# 
############################################################



# MAIN_MEMORY Settings
define_hex CONFIG_XILINX_ERAM_START 0x82000000
define_hex CONFIG_XILINX_ERAM_SIZE 0x02000000

# LMB_MEMORY Settings
define_hex CONFIG_XILINX_LMB_START 0x00000000
define_hex CONFIG_XILINX_LMB_SIZE 0x00002000

# System Clock Frequency
define_int CONFIG_XILINX_CPU_CLOCK_FREQ 100000000

# Definitions for MICROBLAZE0
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_string CONFIG_XILINX_MICROBLAZE0_FAMILY virtex2p
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_int CONFIG_XILINX_MICROBLAZE0_D_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_D_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_BARREL 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_DIV 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR 0
define_int CONFIG_XILINX_MICROBLAZE0_UNALIGNED_EXCEPTIONS 0
define_int CONFIG_XILINX_MICROBLAZE0_ILL_OPCODE_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_IOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DIV_ZERO_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DEBUG_ENABLED 1
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_PBRK 2
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK 1
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK 1
define_int CONFIG_XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE 0
define_int CONFIG_XILINX_MICROBLAZE0_EDGE_IS_POSITIVE 1
define_int CONFIG_XILINX_MICROBLAZE0_FSL_LINKS 0
define_int CONFIG_XILINX_MICROBLAZE0_FSL_DATA_SIZE 32
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR 0x82000000
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR 0x83FFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_ICACHE 1
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_ICACHE_WR 1
define_int CONFIG_XILINX_MICROBLAZE0_ADDR_TAG_BITS 12
define_int CONFIG_XILINX_MICROBLAZE0_CACHE_BYTE_SIZE 8192
define_int CONFIG_XILINX_MICROBLAZE0_ICACHE_USE_FSL 0
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR 0x82000000
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR 0x83FFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_DCACHE 1
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_DCACHE_WR 1
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_ADDR_TAG 12
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE 8192
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_USE_FSL 0
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_string CONFIG_XILINX_MICROBLAZE0_HW_VER 3.00.a

# Definitions for LMB_BRAM_IF_CNTLR_0
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR 0x00001FFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_MASK 0x03C00000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER 1.00.b

# Definitions for LMB_BRAM_IF_CNTLR_1
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR 0x00001FFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_MASK 0x03C00000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER 1.00.b

# Definitions for MDM_0
define_string CONFIG_XILINX_MDM_0_INSTANCE debug_module
define_hex CONFIG_XILINX_MDM_0_BASEADDR 0x80800000
define_hex CONFIG_XILINX_MDM_0_HIGHADDR 0x8080FFFF
define_int CONFIG_XILINX_MDM_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_MDM_0_OPB_AWIDTH 32
define_string CONFIG_XILINX_MDM_0_FAMILY virtex2p
define_int CONFIG_XILINX_MDM_0_MB_DBG_PORTS 1
define_int CONFIG_XILINX_MDM_0_USE_UART 1
define_int CONFIG_XILINX_MDM_0_UART_WIDTH 8
define_int CONFIG_XILINX_MDM_0_WRITE_FSL_PORTS 0
define_string CONFIG_XILINX_MDM_0_INSTANCE debug_module
define_string CONFIG_XILINX_MDM_0_HW_VER 2.00.a

# Definitions for UARTLITE_0
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232
define_hex CONFIG_XILINX_UARTLITE_0_BASEADDR 0x81810000
define_hex CONFIG_XILINX_UARTLITE_0_HIGHADDR 0x8181FFFF
define_int CONFIG_XILINX_UARTLITE_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_DATA_BITS 8
define_int CONFIG_XILINX_UARTLITE_0_CLK_FREQ 100000000
define_int CONFIG_XILINX_UARTLITE_0_BAUDRATE 57600
define_int CONFIG_XILINX_UARTLITE_0_USE_PARITY 0
define_int CONFIG_XILINX_UARTLITE_0_ODD_PARITY 0
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232
define_string CONFIG_XILINX_UARTLITE_0_HW_VER 1.00.b
define_int CONFIG_XILINX_UARTLITE_0_IRQ 2

# Definitions for ETHERNETLITE_0
define_string CONFIG_XILINX_ETHERNETLITE_0_INSTANCE Ethernet_MAC
define_int CONFIG_XILINX_ETHERNETLITE_0_DUPLEX 1
define_int CONFIG_XILINX_ETHERNETLITE_0_RX_PING_PONG 0
define_int CONFIG_XILINX_ETHERNETLITE_0_TX_PING_PONG 0
define_hex CONFIG_XILINX_ETHERNETLITE_0_BASEADDR 0x81410000
define_hex CONFIG_XILINX_ETHERNETLITE_0_HIGHADDR 0x8141FFFF
define_int CONFIG_XILINX_ETHERNETLITE_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_ETHERNETLITE_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_ETHERNETLITE_0_OPB_CLK_PERIOD_PS 10000
define_string CONFIG_XILINX_ETHERNETLITE_0_FAMILY virtex2p
define_string CONFIG_XILINX_ETHERNETLITE_0_INSTANCE Ethernet_MAC
define_string CONFIG_XILINX_ETHERNETLITE_0_HW_VER 1.01.b
define_int CONFIG_XILINX_ETHERNETLITE_0_IRQ 1

# Definitions for GPIO_0
define_string CONFIG_XILINX_GPIO_0_INSTANCE LEDs_4Bit
define_hex CONFIG_XILINX_GPIO_0_BASEADDR 0x80400000
define_hex CONFIG_XILINX_GPIO_0_HIGHADDR 0x8040FFFF
define_int CONFIG_XILINX_GPIO_0_USER_ID_CODE 3
define_int CONFIG_XILINX_GPIO_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_GPIO_0_OPB_DWIDTH 32
define_string CONFIG_XILINX_GPIO_0_FAMILY virtex2p
define_int CONFIG_XILINX_GPIO_0_GPIO_WIDTH 4
define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS 0
define_int CONFIG_XILINX_GPIO_0_INTERRUPT_PRESENT 0
define_int CONFIG_XILINX_GPIO_0_IS_BIDIR 0
define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT 0x00000000
define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT 0xFFFFFFFF
define_int CONFIG_XILINX_GPIO_0_IS_DUAL 0
define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS_2 0
define_int CONFIG_XILINX_GPIO_0_IS_BIDIR_2 1
define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT_2 0x00000000
define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT_2 0xFFFFFFFF
define_string CONFIG_XILINX_GPIO_0_INSTANCE LEDs_4Bit
define_string CONFIG_XILINX_GPIO_0_HW_VER 3.01.b

# Definitions for SDRAM_0
define_string CONFIG_XILINX_SDRAM_0_INSTANCE SDRAM_8Mx32
define_int CONFIG_XILINX_SDRAM_0_INCLUDE_BURST_SUPPORT 1
define_int CONFIG_XILINX_SDRAM_0_INCLUDE_HIGHSPEED_PIPE 0
define_int CONFIG_XILINX_SDRAM_0_USE_POSEDGE_OUTREGS 0
define_string CONFIG_XILINX_SDRAM_0_FAMILY virtex2p
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TMRD 2
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TWR 15000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TCCD 1
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRAS 48000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRC 70000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRFC 75000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRCD 19000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRRD 16000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRP 19000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TREF 64
define_int CONFIG_XILINX_SDRAM_0_SDRAM_REFRESH_NUMROWS 8192
define_int CONFIG_XILINX_SDRAM_0_SDRAM_CAS_LAT 2
define_int CONFIG_XILINX_SDRAM_0_SDRAM_DWIDTH 32
define_int CONFIG_XILINX_SDRAM_0_SDRAM_AWIDTH 12
define_int CONFIG_XILINX_SDRAM_0_SDRAM_COL_AWIDTH 9
define_int CONFIG_XILINX_SDRAM_0_SDRAM_BANK_AWIDTH 2
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TREFI 7812500
define_hex CONFIG_XILINX_SDRAM_0_BASEADDR 0x82000000
define_hex CONFIG_XILINX_SDRAM_0_HIGHADDR 0x83FFFFFF
define_int CONFIG_XILINX_SDRAM_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_SDRAM_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_SDRAM_0_OPB_CLK_PERIOD_PS 10000
define_int CONFIG_XILINX_SDRAM_0_SIM_INIT_TIME_PS 100000000
define_string CONFIG_XILINX_SDRAM_0_INSTANCE SDRAM_8Mx32
define_string CONFIG_XILINX_SDRAM_0_HW_VER 1.00.e

# Definitions for INTC_0
define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
define_string CONFIG_XILINX_INTC_0_FAMILY virtex2p
define_int CONFIG_XILINX_INTC_0_Y 0
define_int CONFIG_XILINX_INTC_0_X 0
define_string CONFIG_XILINX_INTC_0_U_SET intc
define_int CONFIG_XILINX_INTC_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_INTC_0_OPB_DWIDTH 32
define_hex CONFIG_XILINX_INTC_0_BASEADDR 0x81000000
define_hex CONFIG_XILINX_INTC_0_HIGHADDR 0x8100FFFF
define_int CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS 3
define_hex CONFIG_XILINX_INTC_0_KIND_OF_INTR 0x00000006
define_hex CONFIG_XILINX_INTC_0_KIND_OF_EDGE 0x00000006
define_hex CONFIG_XILINX_INTC_0_KIND_OF_LVL 0x00000001
define_int CONFIG_XILINX_INTC_0_HAS_IPR 1
define_int CONFIG_XILINX_INTC_0_HAS_SIE 1
define_int CONFIG_XILINX_INTC_0_HAS_CIE 1
define_int CONFIG_XILINX_INTC_0_HAS_IVR 1
define_int CONFIG_XILINX_INTC_0_IRQ_IS_LEVEL 1
define_int CONFIG_XILINX_INTC_0_IRQ_ACTIVE 1
define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
define_string CONFIG_XILINX_INTC_0_HW_VER 1.00.c

# Peripheral counts
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES 2
define_int CONFIG_XILINX_ETHERNETLITE_NUM_INSTANCES 1
define_int CONFIG_XILINX_INTC_NUM_INSTANCES 1
define_int CONFIG_XILINX_UARTLITE_NUM_INSTANCES 1
define_int CONFIG_XILINX_MDM_NUM_INSTANCES 1
define_int CONFIG_XILINX_SDRAM_NUM_INSTANCES 1
define_int CONFIG_XILINX_GPIO_NUM_INSTANCES 1

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  - From: Andreas Roland

References:
- Re: [microblaze-uclinux] Uclinux + ml403
  - From: mcnernbm
- Re: [microblaze-uclinux] Uclinux + ml403
  - From: John Williams

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