Re: [microblaze-uclinux] Memec S3-1500 board + P160 comms 2

[John Williams <jwilliams@xxxxxxxxxxxxxx>]

I wrote:

> However, when placed in this slot, the P160 MAC phy_rx_d<3> pin, defined 
> as 3.3V LVCMOS, connects to FPGA pin AD13, which is on the same IO bank 
> as most of the main board's DDR signals which are 2.5V SSTL.  e.g.:

A very helpful Insight engineer has helped to resolve this one.  It's 
just a case of changing the IOSTD constraint to LVCMOS25, and trusting 
the source termination resistors on the P160 module to sufficiently 
reduce the 3.3V driving voltages down to the IO's clamping/protection 
thresholds.  This Xilinx answer says more:

http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=yes&getPagePath=20492

Cheers,

John


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