[microblaze-uclinux] Microblaze interrupt registers

[alucero@xxxxxxxxx]

Hi,

My kernel arrives until calibration_delay, then stalls. I'm doing some tests 
with the interrupt controller and I have seen some rare behaviours. 

1) When I write the SIE register to enable interrupts, and after that I read 
the IER register, just the first two bit can be actived. Is it possible that 
IER register just has the neccesary bits for a specific design?

2) If I have the MER with ME actived but without HIE (Hardware Enabled), one 
interrupt enabled, and then I write the ISR for the same interrupt, an 
interrupt should happen with microblaze jumping to 0x00000010 address. I 
don't know why this is not the behaviour, so I'll be happy if someone can 
tell me what I'm doing wrongly. I attach my .mhs and .mss files (I suspect my 
configuration could be incomplete).

Thanks.

-- 
Alejandro Lucero
OS3, OS Serveis i Solucions
www.os3sl.com
Ingeniería Informática
+34 665687168
Av.Benjamin Franklin
CEEI. Parque Tecnológico de Paterna
Valencia(Spain)

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