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[microblaze-uclinux] Crash in timer bottom half -- run_timer_list ()

To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] Crash in timer bottom half -- run_timer_list ()
From: Richard Sewell <Richard.Sewell@xxxxxxxxxx>
Date: Mon, 11 Jul 2005 20:13:41 +0100
Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxx
Hi,

I'm getting uClinux up and running on a custom platform, and am find a crash
in the run_timer_list part of the timer interrupt handler bottom half. Does
anyone know of an obvious cause for this problem? I apologise that I've not
got more detail than that.

If I comment this out, the crash goes away, but obviously I don't get that
far! Any ideas appreciated...

Thanks,

Richard

Here are my auto-config.in and mhs files:


system.mhs

#
############################################################################
##
# Created by Base System Builder Wizard for Xilinx EDK 6.3 Build
EDK_Gmm.12.3
# Fri Jul 01 10:51:03 2005
# Target Board:  Custom
# Family:	 spartan3
# Device:	 xc3s2000
# Package:	 fg676
# Speed Grade:	 -5
# Processor: Microblaze
# System clock frequency: 60.680000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory :   8 KB
# Total Off Chip Memory :  64 MB
# - Generic_SDRAM =  64 MB
#
############################################################################
##


 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_req_to_send_pin = net_gnd, DIR = OUT
 PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = IN
 PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = OUT
 PORT fpga_0_Generic_SDRAM_SDRAM_DQ_pin = fpga_0_Generic_SDRAM_SDRAM_DQ, VEC
= [0:15], DIR = INOUT
 PORT fpga_0_Generic_SDRAM_SDRAM_Addr_pin = fpga_0_Generic_SDRAM_SDRAM_Addr,
VEC = [0:11], DIR = OUT
 PORT fpga_0_Generic_SDRAM_SDRAM_DQM_pin = fpga_0_Generic_SDRAM_SDRAM_DQM,
VEC = [0:1], DIR = OUT
 PORT fpga_0_Generic_SDRAM_SDRAM_WEn_pin = fpga_0_Generic_SDRAM_SDRAM_WEn,
DIR = OUT
 PORT fpga_0_Generic_SDRAM_SDRAM_CKE_pin = fpga_0_Generic_SDRAM_SDRAM_CKE,
DIR = OUT
 PORT fpga_0_Generic_SDRAM_SDRAM_CSn_pin = fpga_0_Generic_SDRAM_SDRAM_CSn,
DIR = OUT
 PORT fpga_0_Generic_SDRAM_SDRAM_CASn_pin = fpga_0_Generic_SDRAM_SDRAM_CASn,
DIR = OUT
 PORT fpga_0_Generic_SDRAM_SDRAM_RASn_pin = fpga_0_Generic_SDRAM_SDRAM_RASn,
DIR = OUT
 PORT fpga_0_Generic_SDRAM_SDRAM_Clk_pin = fpga_0_Generic_SDRAM_SDRAM_Clk,
DIR = OUT
 PORT fpga_0_Generic_SDRAM_SDRAM_BankAddr_pin =
fpga_0_Generic_SDRAM_SDRAM_BankAddr, VEC = [0:1], DIR = OUT
 PORT sys_clk_pin = dcm_clk_s, DIR = IN
 PORT sys_rst_pin = sys_rst_s, DIR = IN
 PORT fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_clk_pin =
fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_clk, DIR = IN
 PORT fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_clk_pin =
fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_clk, DIR = IN
 PORT fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_crs_pin =
fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_crs, DIR = IN
 PORT fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_dv_pin =
fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_dv, DIR = IN
 PORT fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_data_pin =
fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_data, VEC = [3:0], DIR =
IN
 PORT fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_col_pin =
fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_col, DIR = IN
 PORT fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_er_pin =
fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_er, DIR = IN
 PORT fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_en_pin =
fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_en, DIR = OUT
 PORT fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_data_pin =
fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_data, VEC = [3:0], DIR =
OUT
 PORT fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_Mii_clk_pin =
fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_Mii_clk, DIR = INOUT
 PORT fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rst_n_pin =
fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rst_n, DIR = OUT
 PORT fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_Mii_data_pin =
fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_Mii_data, DIR = INOUT
 PORT fpga_0_LEDS_GPIO_d_out_pin = fpga_0_LEDS_GPIO_d_out, VEC = [7:0], DIR
= INOUT


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 4.00.a
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
 PARAMETER C_FSL_LINKS = 1
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_DIV = 1
 PARAMETER C_USE_MSR_INSTR = 1
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 BUS_INTERFACE SFSL0 = fsl_v20_0
 PORT CLK = sys_clk_s
 PORT INTERRUPT = interrupt
 PORT DBG_CAPTURE = DBG_CAPTURE_s
 PORT DBG_CLK = DBG_CLK_s
 PORT DBG_REG_EN = DBG_REG_EN_s
 PORT DBG_TDI = DBG_TDI_s
 PORT DBG_TDO = DBG_TDO_s
 PORT DBG_UPDATE = DBG_UPDATE_s
END

BEGIN opb_v20
 PARAMETER INSTANCE = mb_opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT OPB_Clk = sys_clk_s
END

BEGIN opb_mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x88000000
 PARAMETER C_HIGHADDR = 0x8800ffff
 PARAMETER C_WRITE_FSL_PORTS = 1
 BUS_INTERFACE SOPB = mb_opb
 BUS_INTERFACE MFSL0 = fsl_v20_0
 PORT OPB_Clk = sys_clk_s
 PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
 PORT DBG_CLK_0 = DBG_CLK_s
 PORT DBG_REG_EN_0 = DBG_REG_EN_s
 PORT DBG_TDI_0 = DBG_TDI_s
 PORT DBG_TDO_0 = DBG_TDO_s
 PORT DBG_UPDATE_0 = DBG_UPDATE_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN opb_uartlite
 PARAMETER INSTANCE = RS232
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 1
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_CLK_FREQ = 60683300
 PARAMETER C_BASEADDR = 0x88010000
 PARAMETER C_HIGHADDR = 0x8801ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT RX = fpga_0_RS232_RX
 PORT TX = fpga_0_RS232_TX
 PORT Interrupt = opb_uartlite_Interrupt
END

BEGIN opb_sdram
 PARAMETER INSTANCE = Generic_SDRAM
 PARAMETER HW_VER = 1.00.e
 PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 1
 PARAMETER C_SDRAM_AWIDTH = 12
 PARAMETER C_SDRAM_BANK_AWIDTH = 2
 PARAMETER C_SDRAM_COL_AWIDTH = 8
 PARAMETER C_SDRAM_DWIDTH = 16
 PARAMETER C_OPB_CLK_PERIOD_PS = 16479
 PARAMETER C_SDRAM_TMRD = 2
 PARAMETER C_SDRAM_TCCD = 1
 PARAMETER C_SDRAM_TRAS = 50000
 PARAMETER C_SDRAM_TRC = 70000
 PARAMETER C_SDRAM_TRFC = 80000
 PARAMETER C_SDRAM_TRCD = 20000
 PARAMETER C_SDRAM_TRRD = 20000
 PARAMETER C_SDRAM_TRP = 20000
 PARAMETER C_SDRAM_TREF = 64
 PARAMETER C_SDRAM_CAS_LAT = 3
 PARAMETER C_BASEADDR = 0x8c000000
 PARAMETER C_HIGHADDR = 0x8c7fffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT SDRAM_CLK_in = sys_clk_s
 PORT SDRAM_DQ = fpga_0_Generic_SDRAM_SDRAM_DQ
 PORT SDRAM_Addr = fpga_0_Generic_SDRAM_SDRAM_Addr
 PORT SDRAM_DQM = fpga_0_Generic_SDRAM_SDRAM_DQM
 PORT SDRAM_WEn = fpga_0_Generic_SDRAM_SDRAM_WEn
 PORT SDRAM_CKE = fpga_0_Generic_SDRAM_SDRAM_CKE
 PORT SDRAM_CSn = fpga_0_Generic_SDRAM_SDRAM_CSn
 PORT SDRAM_CASn = fpga_0_Generic_SDRAM_SDRAM_CASn
 PORT SDRAM_RASn = fpga_0_Generic_SDRAM_SDRAM_RASn
 PORT SDRAM_Clk = fpga_0_Generic_SDRAM_SDRAM_Clk
 PORT SDRAM_BankAddr = fpga_0_Generic_SDRAM_SDRAM_BankAddr
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK2X_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 32.959997
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLK2X = sys_clk_s
 PORT CLK0 = dcm_0_FB
 PORT CLKFB = dcm_0_FB
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END

BEGIN opb_ethernet
 PARAMETER INSTANCE = Broadcom_BCM5221_Ethernet_Transceiver
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_DMA_PRESENT = 1
 PARAMETER C_IPIF_RDFIFO_DEPTH = 16384
 PARAMETER C_IPIF_WRFIFO_DEPTH = 16384
 PARAMETER C_OPB_CLK_PERIOD_PS = 16479
 PARAMETER C_DMA_INTR_COALESCE = 1
 PARAMETER C_BASEADDR = 0x88030000
 PARAMETER C_HIGHADDR = 0x8803ffff
 BUS_INTERFACE MSOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT IP2INTC_Irpt = Broadcom_BCM5221_Ethernet_Transceiver_IP2INTC_Irpt
 PORT PHY_tx_clk = fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_clk
 PORT PHY_rx_clk = fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_clk
 PORT PHY_crs = fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_crs
 PORT PHY_dv = fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_dv
 PORT PHY_rx_data = fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rx_data
 PORT PHY_col = fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_col
 PORT PHY_rx_er = net_gnd
 PORT PHY_tx_en = fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_en
 PORT PHY_tx_data = fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_tx_data
 PORT PHY_Mii_clk = fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_Mii_clk
 PORT PHY_rst_n = fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_rst_n
 PORT PHY_Mii_data =
fpga_0_Broadcom_BCM5221_Ethernet_Transceiver_PHY_Mii_data
END

BEGIN opb_timer
 PARAMETER INSTANCE = opb_timer_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 0
 PARAMETER C_BASEADDR = 0x41c00000
 PARAMETER C_HIGHADDR = 0x41c0ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT Interrupt = opb_timer_1_Interrupt
END

BEGIN opb_intc
 PARAMETER INSTANCE = opb_intc_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_BASEADDR = 0x41200000
 PARAMETER C_HIGHADDR = 0x4120ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT Irq = interrupt
 PORT Intr = Broadcom_BCM5221_Ethernet_Transceiver_IP2INTC_Irpt &
opb_uartlite_Interrupt & opb_timer_1_Interrupt
END

BEGIN opb_gpio
 PARAMETER INSTANCE = opb_gpio_0
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000ffff
 PARAMETER C_GPIO_WIDTH = 8
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT GPIO_IO = fpga_0_LEDS_GPIO_d_out
END

BEGIN fsl_v20
 PARAMETER INSTANCE = fsl_v20_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT FSL_Clk = sys_clk_s
END


auto-config.in

############################################################
# 
# CAUTION: This file is automatically generated by libgen.
# Version: Xilinx EDK 7.1.1 EDK_H.11.3 
# Description: uClinux Configuration File
# 
############################################################



# MAIN_MEMORY Settings
define_hex CONFIG_XILINX_ERAM_START 0x8c000000
define_hex CONFIG_XILINX_ERAM_SIZE 0x00800000

# LMB_MEMORY Settings
define_hex CONFIG_XILINX_LMB_START 0x00000000
define_hex CONFIG_XILINX_LMB_SIZE 0x00002000

# System Clock Frequency
define_int CONFIG_XILINX_CPU_CLOCK_FREQ 65919994

# Definitions for MICROBLAZE0
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_string CONFIG_XILINX_MICROBLAZE0_FAMILY spartan3
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_int CONFIG_XILINX_MICROBLAZE0_D_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_D_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_BARREL 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_DIV 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_FPU 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR 0
define_int CONFIG_XILINX_MICROBLAZE0_UNALIGNED_EXCEPTIONS 0
define_int CONFIG_XILINX_MICROBLAZE0_ILL_OPCODE_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_IOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DIV_ZERO_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_FPU_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DEBUG_ENABLED 1
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_PBRK 2
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK 1
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK 1
define_int CONFIG_XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE 0
define_int CONFIG_XILINX_MICROBLAZE0_EDGE_IS_POSITIVE 1
define_int CONFIG_XILINX_MICROBLAZE0_FSL_LINKS 1
define_int CONFIG_XILINX_MICROBLAZE0_FSL_DATA_SIZE 32
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR 0x00000000
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR 0x3FFFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_ICACHE 0
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_ICACHE_WR 1
define_int CONFIG_XILINX_MICROBLAZE0_ADDR_TAG_BITS 17
define_int CONFIG_XILINX_MICROBLAZE0_CACHE_BYTE_SIZE 8192
define_int CONFIG_XILINX_MICROBLAZE0_ICACHE_USE_FSL 0
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR 0x00000000
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR 0x3FFFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_DCACHE 0
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_DCACHE_WR 1
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_ADDR_TAG 17
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE 8192
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_USE_FSL 0
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_string CONFIG_XILINX_MICROBLAZE0_HW_VER 4.00.a

# Definitions for LMB_BRAM_IF_CNTLR_0
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR 0x00001FFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_MASK 0x48000000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER 1.00.b

# Definitions for LMB_BRAM_IF_CNTLR_1
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR 0x00001FFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_MASK 0x48000000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER 1.00.b

# Definitions for MDM_0
define_string CONFIG_XILINX_MDM_0_INSTANCE debug_module
define_hex CONFIG_XILINX_MDM_0_BASEADDR 0x88000000
define_hex CONFIG_XILINX_MDM_0_HIGHADDR 0x8800FFFF
define_int CONFIG_XILINX_MDM_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_MDM_0_OPB_AWIDTH 32
define_string CONFIG_XILINX_MDM_0_FAMILY spartan3
define_int CONFIG_XILINX_MDM_0_MB_DBG_PORTS 1
define_int CONFIG_XILINX_MDM_0_USE_UART 1
define_int CONFIG_XILINX_MDM_0_UART_WIDTH 8
define_int CONFIG_XILINX_MDM_0_WRITE_FSL_PORTS 1
define_string CONFIG_XILINX_MDM_0_INSTANCE debug_module
define_string CONFIG_XILINX_MDM_0_HW_VER 2.00.a

# Definitions for UARTLITE_0
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232
define_hex CONFIG_XILINX_UARTLITE_0_BASEADDR 0x88010000
define_hex CONFIG_XILINX_UARTLITE_0_HIGHADDR 0x8801FFFF
define_int CONFIG_XILINX_UARTLITE_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_DATA_BITS 8
define_int CONFIG_XILINX_UARTLITE_0_CLK_FREQ 60683300
define_int CONFIG_XILINX_UARTLITE_0_BAUDRATE 9600
define_int CONFIG_XILINX_UARTLITE_0_USE_PARITY 0
define_int CONFIG_XILINX_UARTLITE_0_ODD_PARITY 1
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232
define_string CONFIG_XILINX_UARTLITE_0_HW_VER 1.00.b
define_int CONFIG_XILINX_UARTLITE_0_IRQ 1

# Definitions for SDRAM_0
define_string CONFIG_XILINX_SDRAM_0_INSTANCE Generic_SDRAM
define_int CONFIG_XILINX_SDRAM_0_INCLUDE_BURST_SUPPORT 1
define_int CONFIG_XILINX_SDRAM_0_INCLUDE_HIGHSPEED_PIPE 1
define_int CONFIG_XILINX_SDRAM_0_USE_POSEDGE_OUTREGS 0
define_string CONFIG_XILINX_SDRAM_0_FAMILY spartan3
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TMRD 2
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TWR 15000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TCCD 1
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRAS 50000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRC 70000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRFC 80000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRCD 20000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRRD 20000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRP 20000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TREF 64
define_int CONFIG_XILINX_SDRAM_0_SDRAM_REFRESH_NUMROWS 8192
define_int CONFIG_XILINX_SDRAM_0_SDRAM_CAS_LAT 3
define_int CONFIG_XILINX_SDRAM_0_SDRAM_DWIDTH 16
define_int CONFIG_XILINX_SDRAM_0_SDRAM_AWIDTH 12
define_int CONFIG_XILINX_SDRAM_0_SDRAM_COL_AWIDTH 8
define_int CONFIG_XILINX_SDRAM_0_SDRAM_BANK_AWIDTH 2
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TREFI 7812500
define_hex CONFIG_XILINX_SDRAM_0_BASEADDR 0x8C000000
define_hex CONFIG_XILINX_SDRAM_0_HIGHADDR 0x8C7FFFFF
define_int CONFIG_XILINX_SDRAM_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_SDRAM_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_SDRAM_0_OPB_CLK_PERIOD_PS 16479
define_int CONFIG_XILINX_SDRAM_0_SIM_INIT_TIME_PS 100000000
define_string CONFIG_XILINX_SDRAM_0_INSTANCE Generic_SDRAM
define_string CONFIG_XILINX_SDRAM_0_HW_VER 1.00.e

# Definitions for ETHERNET_0
define_string CONFIG_XILINX_ETHERNET_0_INSTANCE
Broadcom_BCM5221_Ethernet_Transceiver
define_int CONFIG_XILINX_ETHERNET_0_DEV_BLK_ID 1
define_int CONFIG_XILINX_ETHERNET_0_DEV_MIR_ENABLE 1
define_hex CONFIG_XILINX_ETHERNET_0_BASEADDR 0x88030000
define_hex CONFIG_XILINX_ETHERNET_0_HIGHADDR 0x8803FFFF
define_int CONFIG_XILINX_ETHERNET_0_RESET_PRESENT 1
define_int CONFIG_XILINX_ETHERNET_0_INCLUDE_DEV_PENCODER 1
define_int CONFIG_XILINX_ETHERNET_0_DMA_PRESENT 1
define_int CONFIG_XILINX_ETHERNET_0_DMA_INTR_COALESCE 1
define_int CONFIG_XILINX_ETHERNET_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_ETHERNET_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_ETHERNET_0_OPB_CLK_PERIOD_PS 16479
define_string CONFIG_XILINX_ETHERNET_0_FAMILY spartan3
define_int CONFIG_XILINX_ETHERNET_0_IPIF_RDFIFO_DEPTH 16384
define_int CONFIG_XILINX_ETHERNET_0_IPIF_WRFIFO_DEPTH 16384
define_hex CONFIG_XILINX_ETHERNET_0_MIIM_CLKDVD 0x0000001F
define_int CONFIG_XILINX_ETHERNET_0_SOURCE_ADDR_INSERT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_PAD_INSERT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_FCS_INSERT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_MAFIFO_DEPTH 64
define_int CONFIG_XILINX_ETHERNET_0_MAFIFO_BRAM_1_SRL_0 0
define_int CONFIG_XILINX_ETHERNET_0_HALF_DUPLEX_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_ERR_COUNT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_CAM_EXIST 0
define_int CONFIG_XILINX_ETHERNET_0_CAM_BRAM_0_SRL_1 1
define_int CONFIG_XILINX_ETHERNET_0_JUMBO_EXIST 0
define_int CONFIG_XILINX_ETHERNET_0_MII_EXIST 1
define_string CONFIG_XILINX_ETHERNET_0_INSTANCE
Broadcom_BCM5221_Ethernet_Transceiver
define_string CONFIG_XILINX_ETHERNET_0_HW_VER 1.02.a
define_int CONFIG_XILINX_ETHERNET_0_IRQ 2

# Definitions for TIMER_0
define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_1
define_string CONFIG_XILINX_TIMER_0_FAMILY spartan3
define_int CONFIG_XILINX_TIMER_0_COUNT_WIDTH 32
define_int CONFIG_XILINX_TIMER_0_ONE_TIMER_ONLY 0
define_int CONFIG_XILINX_TIMER_0_TRIG0_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_TRIG1_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_GEN0_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_GEN1_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_TIMER_0_OPB_DWIDTH 32
define_hex CONFIG_XILINX_TIMER_0_BASEADDR 0x41C00000
define_hex CONFIG_XILINX_TIMER_0_HIGHADDR 0x41C0FFFF
define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_1
define_string CONFIG_XILINX_TIMER_0_HW_VER 1.00.b
define_int CONFIG_XILINX_TIMER_0_IRQ 0

# Definitions for INTC_0
define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
define_string CONFIG_XILINX_INTC_0_FAMILY spartan3
define_int CONFIG_XILINX_INTC_0_Y 0
define_int CONFIG_XILINX_INTC_0_X 0
define_string CONFIG_XILINX_INTC_0_U_SET intc
define_int CONFIG_XILINX_INTC_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_INTC_0_OPB_DWIDTH 32
define_hex CONFIG_XILINX_INTC_0_BASEADDR 0x41200000
define_hex CONFIG_XILINX_INTC_0_HIGHADDR 0x4120FFFF
define_int CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS 3
define_hex CONFIG_XILINX_INTC_0_KIND_OF_INTR 0x00000002
define_hex CONFIG_XILINX_INTC_0_KIND_OF_EDGE 0x00000002
define_hex CONFIG_XILINX_INTC_0_KIND_OF_LVL 0x00000005
define_int CONFIG_XILINX_INTC_0_HAS_IPR 1
define_int CONFIG_XILINX_INTC_0_HAS_SIE 1
define_int CONFIG_XILINX_INTC_0_HAS_CIE 1
define_int CONFIG_XILINX_INTC_0_HAS_IVR 1
define_int CONFIG_XILINX_INTC_0_IRQ_IS_LEVEL 1
define_int CONFIG_XILINX_INTC_0_IRQ_ACTIVE 1
define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
define_string CONFIG_XILINX_INTC_0_HW_VER 1.00.c

# Definitions for GPIO_0
define_string CONFIG_XILINX_GPIO_0_INSTANCE opb_gpio_0
define_hex CONFIG_XILINX_GPIO_0_BASEADDR 0x40000000
define_hex CONFIG_XILINX_GPIO_0_HIGHADDR 0x4000FFFF
define_int CONFIG_XILINX_GPIO_0_USER_ID_CODE 3
define_int CONFIG_XILINX_GPIO_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_GPIO_0_OPB_DWIDTH 32
define_string CONFIG_XILINX_GPIO_0_FAMILY spartan3
define_int CONFIG_XILINX_GPIO_0_GPIO_WIDTH 8
define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS 0
define_int CONFIG_XILINX_GPIO_0_INTERRUPT_PRESENT 0
define_int CONFIG_XILINX_GPIO_0_IS_BIDIR 1
define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT 0x00000000
define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT 0xFFFFFFFF
define_int CONFIG_XILINX_GPIO_0_IS_DUAL 0
define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS_2 0
define_int CONFIG_XILINX_GPIO_0_IS_BIDIR_2 1
define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT_2 0x00000000
define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT_2 0xFFFFFFFF
define_string CONFIG_XILINX_GPIO_0_INSTANCE opb_gpio_0
define_string CONFIG_XILINX_GPIO_0_HW_VER 3.01.b

# Peripheral counts
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES 2
define_int CONFIG_XILINX_TIMER_NUM_INSTANCES 1
define_int CONFIG_XILINX_INTC_NUM_INSTANCES 1
define_int CONFIG_XILINX_UARTLITE_NUM_INSTANCES 1
define_int CONFIG_XILINX_MDM_NUM_INSTANCES 1
define_int CONFIG_XILINX_GPIO_NUM_INSTANCES 1
define_int CONFIG_XILINX_ETHERNET_NUM_INSTANCES 1
define_int CONFIG_XILINX_SDRAM_NUM_INSTANCES 1


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