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[microblaze-uclinux] KErnel Boot Error on Spartan IIE LC 600

To: microblaze-uClinux <microblaze-uclinux@xxxxxxxxxxxxxx>
Subject: [microblaze-uclinux] KErnel Boot Error on Spartan IIE LC 600
From: calayrac@xxxxxxxxxxxxxxx
Date: Fri, 29 Jul 2005 10:11:42 +0200
Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxx
User-agent: Internet Messaging Program (IMP) 3.2.1


Hi John,

I've make progress in my project but the kernel stay hang after the famous
Calibrating delay loop...

I've a quick look in email archive and found that some of us already face that 
problem. Your recommendation at that ttime was that external memory should fit 
he real size of the one embed on the board (my own as 32MB SDRAM), and to 
check interrupt.

I've check all that point unsucessfully. 
I'm afraid there is a problem with cach memory because I resize it to 8k (16k 
on your original design uclinux_auto_6_30_b)

The complete bootlog sequence is: (please scroll down due to blank line!!!)
------------------------------------------------------------------------------
Linux version 2.4.31-uc0 (alayrac@debian-labo) (gcc version 2.95.3-4 Xilinx EDK
6.3 Build EDK_Gmm.12.2) #10 jeu jui 28 18:48:51 CEST 
2005                                                         

On node 0 totalpages: 8192                          

zone(0): 8192 pages.                    

zone(1): 0 pages.                 

zone(2): 0 pages.                 

CPU: MICROBLAZE               

Kernel command line: º                      






























€

Console: xmbserial on UARTLite

Calibrating delay loop...
-------------------------------------------------------------------------------

As you can see there is a strange sequence after Kernel Command Line.

I include MHS and MSS files from my design in case you can identify any 
mistake.

I'm out of the office the next four weeks so my request is not very urgent.
Thank you in advance for your help

Regards

Christophe



# ##############################################################################
# Target Board:	 Memec Design Virtex-2 1000  Development Board
# with P160 Comm Module
# Family:	     virtex2
# Device:	     XCV21000
# Package:
# Speed Grade:	 -6
# Processor:     Microblaze
# Debug interface: On-Chip HW Debug Module
# On Chip Memory :   16 KB
# Total Off Chip Memory :  32 MB
# - SDRAM_8Mx32 =  32 MB
# ##############################################################################
# Parameters
 PARAMETER VERSION = 2.1.0


 PORT ext_clk = ext_clk, DIR = IN
 PORT ddr_clk_fb = ddr_clk_fb, DIR = IN
 PORT sys_rst = sys_rst, DIR = IN
 PORT console_uart_rx = console_uart_rx, DIR = IN
 PORT console_uart_tx = console_uart_tx, DIR = OUT
 PORT sram_cen = sram_cen, VEC = [0:1], DIR = OUT
 PORT sram_addr = sram_addr, VEC = [10:29], DIR = OUT
 PORT sram_ben = sram_ben, VEC = [0:3], DIR = OUT
 PORT sram_data = sram_data, VEC = [0:31], DIR = INOUT
 PORT sram_oen = sram_oen, DIR = OUT
 PORT sram_wen = sram_wen, DIR = OUT
 PORT sram_rst = sram_rpn, DIR = OUT
 PORT gpio = gpio, VEC = [0:23], DIR = INOUT
 PORT SDRAM_DQ = SDRAM_DQ, VEC = [0:31], DIR = INOUT
 PORT SDRAM_Addr = SDRAM_Addr, VEC = [0:11], DIR = OUT
 PORT SDRAM_DQM = SDRAM_DQM, VEC = [0:3], DIR = OUT
 PORT SDRAM_WEn = SDRAM_WEn, DIR = OUT
 PORT SDRAM_CKE = SDRAM_CKE, DIR = OUT
 PORT SDRAM_CSn = SDRAM_CSn, DIR = OUT
 PORT SDRAM_CASn = SDRAM_CASn, DIR = OUT
 PORT SDRAM_RASn = SDRAM_RASn, DIR = OUT
 PORT SDRAM_Clk = SDRAM_Clk, DIR = OUT
 PORT SDRAM_BankAddr = SDRAM_BankAddr, VEC = [0:1], DIR = OUT
 PORT Ethernet_MAC_PHY_tx_er = Ethernet_MAC_PHY_tx_er, DIR = output
 PORT Ethernet_MAC_PHY_tx_clk = Ethernet_MAC_PHY_tx_clk, DIR = input
 PORT Ethernet_MAC_PHY_rx_clk = Ethernet_MAC_PHY_rx_clk, DIR = input
 PORT Ethernet_MAC_PHY_crs = Ethernet_MAC_PHY_crs, DIR = input
 PORT Ethernet_MAC_PHY_dv = Ethernet_MAC_PHY_dv, DIR = input
 PORT Ethernet_MAC_PHY_col = Ethernet_MAC_PHY_col, DIR = input
 PORT Ethernet_MAC_PHY_rx_er = Ethernet_MAC_PHY_rx_er, DIR = input
 PORT Ethernet_MAC_PHY_tx_en = Ethernet_MAC_PHY_tx_en, DIR = output
 PORT Ethernet_MAC_PHY_Mii_clk = Ethernet_MAC_PHY_Mii_clk, DIR = inout
 PORT Ethernet_MAC_PHY_rst_n = Ethernet_MAC_PHY_rst_n, DIR = output
 PORT Ethernet_MAC_PHY_Mii_data = Ethernet_MAC_PHY_Mii_data, DIR = inout
 PORT Ethernet_MAC_PHY_rx_data = Ethernet_MAC_PHY_rx_data, VEC = [3:0], DIR = input
 PORT Ethernet_MAC_PHY_tx_data = Ethernet_MAC_PHY_tx_data, VEC = [3:0], DIR = output


# Sub Components
BEGIN ibufg_clkdll
 PARAMETER INSTANCE = clk100_to_66_6
 PORT sys_clk_raw = ext_clk
 PORT sys_clk_dll = sys_clk
 PORT rst_dll = net_vcc
 PORT locked_dll = locked_dll
END

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_DIV = 1
 PARAMETER C_USE_MSR_INSTR = 1
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_ICACHE_BASEADDR = 0x84000000
 PARAMETER C_ICACHE_HIGHADDR = 0x85FFFFFF
 PARAMETER C_CACHE_BYTE_SIZE = 8192
 PARAMETER C_ADDR_TAG_BITS = 11
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_DCACHE_BASEADDR = 0x84000000
 PARAMETER C_DCACHE_HIGHADDR = 0x85FFFFFF
 PARAMETER C_DCACHE_BYTE_SIZE = 8192
 PARAMETER C_DCACHE_ADDR_TAG = 11
 PARAMETER C_FSL_LINKS = 1
 BUS_INTERFACE SFSL0 = download_link
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 PORT CLK = sys_clk
 PORT INTERRUPT = interrupt
END

BEGIN opb_mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 0
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0xFFFFC000
 PARAMETER C_HIGHADDR = 0xFFFFC0FF
 PARAMETER C_WRITE_FSL_PORTS = 1
 BUS_INTERFACE MFSL0 = download_link
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk
END

BEGIN fsl_v20
 PARAMETER INSTANCE = download_link
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst
 PORT FSL_Clk = sys_clk
END

BEGIN opb_emc
 PARAMETER INSTANCE = sram_flash
 PARAMETER HW_VER = 1.10.b
 PARAMETER C_OPB_CLK_PERIOD_PS = 15000
 PARAMETER C_NUM_BANKS_MEM = 2
 PARAMETER C_MAX_MEM_WIDTH = 32
 PARAMETER C_MEM0_WIDTH = 32
 PARAMETER C_MEM1_WIDTH = 32
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_1 = 0
 PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_0 = 150000
 PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 55000
 PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_0 = 70000
 PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_0 = 150000
 PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 55000
 PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_0 = 15000
 PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_0 = 35000
 PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_1 = 150000
 PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_1 = 55000
 PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_1 = 70000
 PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_1 = 150000
 PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_1 = 55000
 PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_1 = 15000
 PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_1 = 35000
 PARAMETER C_BASEADDR = 0xFFFF0000
 PARAMETER C_HIGHADDR = 0xFFFF01FF
 PARAMETER C_MEM0_BASEADDR = 0xFFE00000
 PARAMETER C_MEM0_HIGHADDR = 0xFFEFFFFF
 PARAMETER C_MEM1_BASEADDR = 0xFF000000
 PARAMETER C_MEM1_HIGHADDR = 0xFF7FFFFF
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk
 PORT Mem_CEN = sram_cen
 PORT Mem_A = sram_addr_full
 PORT Mem_BEN = sram_ben
 PORT Mem_DQ = sram_data
 PORT Mem_OEN = sram_oen_full
 PORT Mem_WEN = sram_wen
 PORT Mem_RPN = sram_rpn
END

BEGIN util_reduced_logic
 PARAMETER INSTANCE = oe_adj
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 2
 PARAMETER C_OPERATION = and
 PORT Op1 = sram_oen_full
 PORT Res = sram_oen
END

BEGIN util_bus_split
 PARAMETER INSTANCE = addr_adj
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE_IN = 32
 PARAMETER C_LEFT_POS = 10
 PARAMETER C_SPLIT = 30
 PORT Sig = sram_addr_full
 PORT Out1 = sram_addr
END

BEGIN opb_uartlite
 PARAMETER INSTANCE = console_uart
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BAUDRATE = 57600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_CLK_FREQ = 66_666_667
 PARAMETER C_BASEADDR = 0xFFFF2000
 PARAMETER C_HIGHADDR = 0xFFFF20FF
 BUS_INTERFACE SOPB = mb_opb
 PORT Interrupt = console_uart_interrupt
 PORT OPB_Clk = sys_clk
 PORT RX = console_uart_rx
 PORT TX = console_uart_tx
END

BEGIN opb_intc
 PARAMETER INSTANCE = system_intc
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_BASEADDR = 0xffff3000
 PARAMETER C_HIGHADDR = 0xffff301f
 BUS_INTERFACE SOPB = mb_opb
 PORT Irq = interrupt
 PORT OPB_Clk = sys_clk
 PORT Intr = Ethernet_MAC_IP2INTC_Irpt & console_uart_interrupt & timer_interrupt
END

BEGIN opb_timer
 PARAMETER INSTANCE = system_timer
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0xffff1000
 PARAMETER C_HIGHADDR = 0xffff10ff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk
 PORT Interrupt = timer_interrupt
END

BEGIN opb_gpio
 PARAMETER INSTANCE = system_gpio
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0xffff5000
 PARAMETER C_HIGHADDR = 0xffff50ff
 PARAMETER C_GPIO_WIDTH = 24
 BUS_INTERFACE SOPB = mb_opb
 PORT GPIO_IO = gpio
 PORT OPB_Clk = sys_clk
END

BEGIN opb_ethernet
 PARAMETER INSTANCE = ethernet
 PARAMETER HW_VER = 1.00.m
 PARAMETER C_DMA_INTR_COALESCE = 1
 PARAMETER C_OPB_CLK_PERIOD_PS = 15000
 PARAMETER C_BASEADDR = 0xC0000000
 PARAMETER C_HIGHADDR = 0xC0003FFF
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk
 PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
 PORT PHY_tx_er = Ethernet_MAC_PHY_tx_er
 PORT PHY_tx_clk = Ethernet_MAC_PHY_tx_clk
 PORT PHY_rx_clk = Ethernet_MAC_PHY_rx_clk
 PORT PHY_crs = Ethernet_MAC_PHY_crs
 PORT PHY_dv = Ethernet_MAC_PHY_dv
 PORT PHY_col = Ethernet_MAC_PHY_col
 PORT PHY_rx_er = Ethernet_MAC_PHY_rx_er
 PORT PHY_tx_en = Ethernet_MAC_PHY_tx_en
 PORT PHY_Mii_clk = Ethernet_MAC_PHY_Mii_clk
 PORT PHY_rst_n = Ethernet_MAC_PHY_rst_n
 PORT PHY_Mii_data = Ethernet_MAC_PHY_Mii_data
 PORT PHY_rx_data = Ethernet_MAC_PHY_rx_data
 PORT PHY_tx_data = Ethernet_MAC_PHY_tx_data
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00000fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = conn_0
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00000fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = conn_1
END

BEGIN bram_block
 PARAMETER INSTANCE = bram
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_MEMSIZE = 8192
 BUS_INTERFACE PORTA = conn_0
 BUS_INTERFACE PORTB = conn_1
END

BEGIN opb_v20
 PARAMETER INSTANCE = mb_opb
 PARAMETER HW_VER = 1.10.b
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT OPB_Clk = sys_clk
 PORT SYS_Rst = sys_rst
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT LMB_Clk = sys_clk
 PORT SYS_Rst = sys_rst
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT LMB_Clk = sys_clk
 PORT SYS_Rst = sys_rst
END

BEGIN opb_sdram
 PARAMETER INSTANCE = ddr_controller
 PARAMETER HW_VER = 1.00.d
 PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 1
 PARAMETER C_OPB_CLK_PERIOD_PS = 15000
 PARAMETER C_SDRAM_TMRD = 2
 PARAMETER C_SDRAM_TCCD = 1
 PARAMETER C_SDRAM_TRAS = 48000
 PARAMETER C_SDRAM_TRC = 70000
 PARAMETER C_SDRAM_TRFC = 75000
 PARAMETER C_SDRAM_TRCD = 19000
 PARAMETER C_SDRAM_TRRD = 16000
 PARAMETER C_SDRAM_TRP = 19000
 PARAMETER C_SDRAM_TREF = 64
 PARAMETER C_SDRAM_CAS_LAT = 2
 PARAMETER C_SDRAM_COL_AWIDTH = 9
 PARAMETER C_SDRAM_BANK_AWIDTH = 2
 PARAMETER C_SDRAM_AWIDTH = 12
 PARAMETER C_SDRAM_DWIDTH = 32
 PARAMETER C_BASEADDR = 0x80000000
 PARAMETER C_HIGHADDR = 0x81ffffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk
 PORT SDRAM_CLK_in = sys_clk
 PORT SDRAM_DQ = SDRAM_DQ
 PORT SDRAM_Addr = SDRAM_Addr
 PORT SDRAM_DQM = SDRAM_DQM
 PORT SDRAM_WEn = SDRAM_WEn
 PORT SDRAM_CKE = SDRAM_CKE
 PORT SDRAM_CSn = SDRAM_CSn
 PORT SDRAM_CASn = SDRAM_CASn
 PORT SDRAM_RASn = SDRAM_RASn
 PORT SDRAM_Clk = SDRAM_Clk
 PORT SDRAM_BankAddr = SDRAM_BankAddr
END


 PARAMETER VERSION = 2.2.0


BEGIN OS
 PARAMETER OS_NAME = uclinux
 PARAMETER OS_VER = 1.00.a
 PARAMETER PROC_INSTANCE = microblaze_0
 PARAMETER MAIN_MEMORY = ddr_controller
 PARAMETER FLASH_MEMORY = sram_flash
 PARAMETER FLASH_MEMORY_BANK = 1
 PARAMETER LMB_MEMORY = ilmb_cntlr
# handlers for the bootloader, not used in uclinux kernel
 PARAMETER STDOUT = console_uart
 PARAMETER STDIN = console_uart
END


# where to copy resulting auto-config.in file
# PARAMETER TARGET_DIR = /mnt/home2/jwilliam/dist-test/uClinux-dist/linux-2.4.x/arch/microblaze/platform/uclinux-auto
BEGIN PROCESSOR
 PARAMETER DRIVER_NAME = cpu
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = microblaze_0
 PARAMETER ARCHIVER = mb-ar
 PARAMETER COMPILER = mb-gcc
 PARAMETER XMDSTUB_PERIPHERAL = debug_module
# 66MHz
 PARAMETER CORE_CLOCK_FREQ_HZ = 66666667
END


BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = debug_module
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = dlmb_cntlr
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = ilmb_cntlr
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = mb_opb
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = intc
 PARAMETER DRIVER_VER = 1.00.c
 PARAMETER HW_INSTANCE = system_intc
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = tmrctr
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = system_timer
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = console_uart
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = system_gpio
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = ddr_controller
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = emac
 PARAMETER DRIVER_VER = 1.00.e
 PARAMETER HW_INSTANCE = ethernet
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = emc
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = sram_flash
 PARAMETER LEVEL = 0
END

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