RE: [microblaze-uclinux] Avnet XCS2000 S3 boot complete

["Siddharth Rele" <siddharth.rele@xxxxxxxxxx>]

The msrclr/msrset issue mentioned in this email has been fixed in EDK 7.1i SP2. This was a bug in MicroBlaze, which has been fixed. Please update to the latest version of EDK Service Pack. Please do note that the latest service pack of EDK works best with the latest service pack of ISE 7.1i (i.e ISE 7.1i Sp3).

Thanks
Sid


> -----Original Message-----
> From: owner-microblaze-uclinux@itee.uq.edu.au [mailto:owner-microblaze-
> uclinux@itee.uq.edu.au] On Behalf Of Paul Hartke
> Sent: Friday, June 24, 2005 2:42 PM
> To: microblaze-uclinux@itee.uq.edu.au
> Subject: Re: [microblaze-uclinux] Avnet XCS2000 S3 boot complete
> 
> I try to build systems with the least amount of options first and then
> slowly add ones after the base configuration is working.
> 
> The XUP-V2P design using Microblaze 4.00.a but only a few simple options
> out
> of Base System Builder.  It was implemented with EDK 7.1 SP1 and ISE 7.1
> SP2
> on a Linux machine.
> 
> Quoting alucero@os3sl.com:
> > Hi,
> >
> > I'm happiest man in the world !  (At least at this exactly moment)
> >
> > I have had some problems, and the boot is succesful but with several
> > limitations:
> >
> > 1) Using msrcrl & msrset instructions the boot stalls at calibrate_delay.
> > After some tests I discovered that msrclr was not working in the right
> > way
> > and the flags stored were 0x0. I have disabled these functions in the
> mhs
> > file (and recompiled the kernel with the new autoconfig) and things were
> > getting better but ...
> >
> > 2) I dont know why but BIP bit (MSR) was actived at the beginning of
> > calibration_delay, so I'm disabling the bit (hardcoded) inside this
> > function.
> > Can someone tell me why this bit is on?
> >
> > 3) Once calibration delay was left behind, the boot stalls at slab.c
> > (682).
> > However, I had discovered before that this does not happen with
> > Microblaze
> > 3.00. So I changed the mhs file from 4.00 to 3.00.
> >
> > And login appered !!!
> >
> > Before this moment, I thought that I could have something wrong in my
> > hardware
> > configuration, since I'm far to be a FPGA programmer expert (this is my
> > first
> > experience with this wonderful world), but as now this is working I
> > suppose
> > my conf in OK. As I know there are people working with msrclr & msrset
> > and
> > with Microblaze 4.00, the question is: are you using ISE 7.1?
> >
> > I try to get a reason for my configuration limitations.
> >
> >
> >
> > --
> > Alejandro Lucero
> > OS3, OS Serveis i Solucions
> > www.os3sl.com
> > Ingeniería Informática
> > +34 665687168
> > Av.Benjamin Franklin
> > CEEI. Parque Tecnológico de Paterna
> > Valencia(Spain)
> >
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> uclinux/
> 



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