Re: [microblaze-uclinux] Microblaze slices and BRAMs optimizationwith uclinux

[John Williams <jwilliams@xxxxxxxxxxxxxx>]

Hi Claudio,

Claudio Lanconelli wrote:

> I need to save some slices and BRAMs to fit my uclinux project into a 
> Spartan3 XC3S400.
> Disabling the ICACHE and DCACHE saves both slices and BRAMs but have a 
> strong impact on the performaces,
> so I'm trying other ways.
> 
> 1)
> Looking at the design report I noticed that the opb_timer takes about 
> 260 slices and seems that uclinux uses only one
> timer, is it true? Can I configure the opb_timer with only one 32bit 
> timer (C_ONE_TIMER_ONLY=1)?

That should be fine - the kernel only uses channel 0 for the system timer.

Also, it should be pretty simple to tweak the kernel to use the FIT 
(fixed interval timer) rather than the programmable timer.  The FIT is 
likely to be a lot smaller than the opb_timer

> 
> 2)
> Xapp482 uses a custom opb_bram_controller to use only 2K of BRAM, is it 
> compatible with uclinux? Does uclinux-auto depends on the 
> lmb_bram_controller in any ways?

Currently rhe kernel makes no use of the LMB memory.  The LMB_MEMORY 
parameter in the MSS file is just for completeness.  You should actually 
be able to set that to "none" without difficulty.

Regards,

John
___________________________
microblaze-uclinux mailing list
microblaze-uclinux@itee.uq.edu.au
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/