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[microblaze-uclinux] why such idiv latency of 34 cycles?
Hi,
please, look at
XilinxEDK6.3i\doc\mb_ref_guide.pdf, Chapter 4 "MicroBlaze Instruction Set
Architecture" where it says:
idiv Integer Divide
Latency
2 cycles if (rA) = 0, otherwise 34 cycles
Why is division that slow?
(Most other instructions have latency around 2)
Such slow division gives us big headaches in the algorithm code.
Cheers
Falk
___________________________________
Falk Brettschneider
Software Developer
http://www.baumeroptronic.de
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