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[microblaze-uclinux] mb+uclinux on ml310
Hello Team,
I am struggling to build a uclinux + microblaze system on ML310 board.
Below is the system I created.
Microblaze with BRAM of 32K and a DDR external mem of 256MB,
a custom IP, UARTLite and LEDs and a single OPB timer.
Correct me below if I am wrong.
The CompactFlash on board ML310 is accessible only through System ACE
CF. And so I have it a SYSACE CF controller included as well.
It doesnt show up as EMC for Flash. So I left the software settings
for FLASH as none.
I get the following error, while building uclinux libraries.
Can anyone help?
--------
#--------------------------------------
# uClinux BSP generate...
#--------------------------------------
Override specified for MAIN_MEMORY:0x10000000
ERROR:MDT - xget_handle 36360928 ipinst none peripheral : xget_handle:
Ip
instance none not found
ERROR:MDT - ERROR FROM TCL:- uclinux () -
while executing
"xget_handle $processor_handle "ipinst" $ipinst_name "peripheral""
(procedure "xget_sw_ipinst_handle_from_processor" line 2)
invoked from within
"xget_sw_ipinst_handle_from_processor $proc_handle $mem"
(procedure "do_memory_setup" line 13)
invoked from within
"do_memory_setup $config_file $os_handle "FLASH_MEMORY"
CONFIG_XILINX_FLASH"
(procedure "::sw_uclinux_v1_00_c::generate" line 23)
invoked from within
"::sw_uclinux_v1_00_c::generate 35492784"
WARNING: The parameter USE_DCR for the intc driver has been
deprecated. Any reference to this parameter in the MSS file will be
ignored.
define_config_file: XNullHandler
Copying Library Files ...
ERROR:MDT - Error while running "generate" for processor
microblaze_0...
make: *** [microblaze_0/lib/libxil.a] Error 2
Done.
------
I have attached the .mhs/.mss file below for your reference.
Please let me know how to correct this error.
I hope someone has had success in builing uclinux + microblaze on
ML310.
I would appreciate much if I have some pointers.
Thanks
LN
PARAMETER VERSION = 2.2.0
BEGIN OS
PARAMETER OS_NAME = uclinux
PARAMETER OS_VER = 1.00.c
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER stdout = RS232_Uart
PARAMETER stdin = RS232_Uart
PARAMETER main_memory = DDR_SDRAM_32Mx64
PARAMETER main_memory_size = 0x10000000
PARAMETER main_memory_bank = 0
PARAMETER lmb_memory = dlmb_cntlr
PARAMETER TARGET_DIR = D:/xilinx/ml310/test_icap/hw/mblaze_uclinux/uclinux
PARAMETER flash_memory_bank = 0
END
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = microblaze_0
PARAMETER COMPILER = mb-gcc
PARAMETER ARCHIVER = mb-ar
PARAMETER CORE_CLOCK_FREQ_HZ = 66666667
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dlmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ilmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = mb_opb
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = RS232_Uart
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ddr
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = DDR_SDRAM_32Mx64
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 2.00.a
PARAMETER HW_INSTANCE = LEDs_8Bit
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = sysace
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = SysACE_CompactFlash
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = intc
PARAMETER DRIVER_VER = 1.00.c
PARAMETER HW_INSTANCE = opb_intc_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dcm_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dcm_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dcm_2
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = opb_hwicap_custom
PARAMETER DRIVER_VER = 1.00.z
PARAMETER HW_INSTANCE = opb_hwicap_custom_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = tmrctr
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = opb_timer_0
END
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 6.3 Build EDK_Gmm.10
# Thu Aug 25 18:41:08 2005
# Target Board: Xilinx Virtex-II Pro ML310 Evaluation Platform Rev D
# Family: virtex2p
# Device: xc2vp30
# Package: ff896
# Speed Grade: -6
# Processor: Microblaze
# System clock frequency: 66.666667 MHz
# Debug interface: No Debug
# On Chip Memory : 32 KB
# Total Off Chip Memory : 256 MB
# - DDR_SDRAM_32Mx64 = 256 MB
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_Clk_pin = fpga_0_DDR_SDRAM_32Mx64_DDR_Clk, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn_pin = fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin = fpga_0_DDR_SDRAM_32Mx64_DDR_Addr, DIR = OUTPUT, VEC = [0:12]
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr, DIR = OUTPUT, VEC = [0:1]
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_CASn_pin = fpga_0_DDR_SDRAM_32Mx64_DDR_CASn, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_CKE_pin = fpga_0_DDR_SDRAM_32Mx64_DDR_CKE, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_CSn_pin = fpga_0_DDR_SDRAM_32Mx64_DDR_CSn, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_RASn_pin = fpga_0_DDR_SDRAM_32Mx64_DDR_RASn, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_WEn_pin = fpga_0_DDR_SDRAM_32Mx64_DDR_WEn, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin = fpga_0_DDR_SDRAM_32Mx64_DDR_DM, DIR = OUTPUT, VEC = [0:1]
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin = fpga_0_DDR_SDRAM_32Mx64_DDR_DQS, DIR = INOUT, VEC = [0:1]
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin = fpga_0_DDR_SDRAM_32Mx64_DDR_DQ, DIR = INOUT, VEC = [0:15]
PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = INPUT
PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = OUTPUT
PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO, DIR = INOUT, VEC = [0:7]
PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = INPUT
PORT fpga_0_SysACE_CompactFlash_clk_enable_n_pin = net_vcc, DIR = OUTPUT
PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = OUTPUT, VEC = [6:0]
PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = INOUT, VEC = [7:0]
PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = OUTPUT
PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = OUTPUT
PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = OUTPUT
PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = INPUT
PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = INPUT
PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = OUTPUT
PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = CLK
PORT sys_rst_pin = sys_rst_s, DIR = INPUT
BEGIN opb_timer
PARAMETER INSTANCE = opb_timer_0
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0xc0001000
PARAMETER C_HIGHADDR = 0xc00010ff
PARAMETER C_ONE_TIMER_ONLY = 1
BUS_INTERFACE SOPB = mb_opb
END
BEGIN opb_intc
PARAMETER INSTANCE = opb_intc_0
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0xa0000000
PARAMETER C_HIGHADDR = 0xa00000ff
BUS_INTERFACE SOPB = mb_opb
PORT Irq = Interrupt
PORT Intr = RS232_Uart_Interrupt & SysACE_CompactFlash_SysACE_IRQ
END
BEGIN opb_hwicap_custom
PARAMETER INSTANCE = opb_hwicap_custom_0
PARAMETER HW_VER = 1.00.z
PARAMETER C_BASEADDR = 0xc0000000
PARAMETER C_HIGHADDR = 0xc00000ff
BUS_INTERFACE SOPB = mb_opb
END
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 3.00.a
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
PORT CLK = sys_clk_s
PORT Interrupt = Interrupt
END
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.b
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT OPB_Clk = sys_clk_s
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00007fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00007fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_2
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK270_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 15.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 0
PORT CLKIN = ddr_feedback_s
PORT CLK90 = ddr_clk_90_s
PORT CLK270 = ddr_clk_90_n_s
PORT CLK0 = dcm_2_FB
PORT CLKFB = dcm_2_FB
PORT RST = dcm_1_lock
PORT LOCKED = dcm_2_lock
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK180_BUF = TRUE
PARAMETER C_CLK270_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 15.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 0
PORT CLKIN = sys_clk_s
PORT CLK90 = clk_90_s
PORT CLK180 = sys_clk_n_s
PORT CLK270 = clk_90_n_s
PORT CLK0 = dcm_1_FB
PORT CLKFB = dcm_1_FB
PORT RST = dcm_0_lock
PORT LOCKED = dcm_1_lock
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLKDV_BUF = TRUE
PARAMETER C_CLKDV_DIVIDE = 1.500000
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLKDV = sys_clk_s
PORT CLK0 = dcm_0_FB
PORT CLKFB = dcm_0_FB
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END
BEGIN opb_sysace
PARAMETER INSTANCE = SysACE_CompactFlash
PARAMETER HW_VER = 1.00.b
PARAMETER C_MEM_WIDTH = 8
PARAMETER C_BASEADDR = 0xa0000100
PARAMETER C_HIGHADDR = 0xa00001ff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ
PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA
PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_Uart
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 66000000
PARAMETER C_BASEADDR = 0xa0000200
PARAMETER C_HIGHADDR = 0xa00002ff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT Interrupt = RS232_Uart_Interrupt
PORT RX = fpga_0_RS232_Uart_RX
PORT TX = fpga_0_RS232_Uart_TX
END
BEGIN opb_gpio
PARAMETER INSTANCE = LEDs_8Bit
PARAMETER HW_VER = 3.01.a
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0xa0000400
PARAMETER C_HIGHADDR = 0xa00005ff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT GPIO_IO = fpga_0_LEDs_8Bit_GPIO_IO
END
BEGIN opb_ddr
PARAMETER INSTANCE = DDR_SDRAM_32Mx64
PARAMETER HW_VER = 1.10.a
PARAMETER C_OPB_CLK_PERIOD_PS = 14999
PARAMETER C_REG_DIMM = 1
PARAMETER C_DDR_TMRD = 20000
PARAMETER C_DDR_TWR = 20000
PARAMETER C_DDR_TRAS = 60000
PARAMETER C_DDR_TRC = 90000
PARAMETER C_DDR_TRFC = 100000
PARAMETER C_DDR_TRCD = 30000
PARAMETER C_DDR_TRRD = 20000
PARAMETER C_DDR_TRP = 30000
PARAMETER C_DDR_TREFC = 70300000
PARAMETER C_DDR_AWIDTH = 13
PARAMETER C_DDR_COL_AWIDTH = 10
PARAMETER C_DDR_BANK_AWIDTH = 2
PARAMETER C_NUM_CLK_PAIRS = 2
PARAMETER C_MEM0_BASEADDR = 0xb0000000
PARAMETER C_MEM0_HIGHADDR = 0xbfffffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT DDR_Addr = fpga_0_DDR_SDRAM_32Mx64_DDR_Addr
PORT DDR_BankAddr = fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr
PORT DDR_CASn = fpga_0_DDR_SDRAM_32Mx64_DDR_CASn
PORT DDR_CKE = fpga_0_DDR_SDRAM_32Mx64_DDR_CKE
PORT DDR_CSn = fpga_0_DDR_SDRAM_32Mx64_DDR_CSn
PORT DDR_RASn = fpga_0_DDR_SDRAM_32Mx64_DDR_RASn
PORT DDR_WEn = fpga_0_DDR_SDRAM_32Mx64_DDR_WEn
PORT DDR_DM = fpga_0_DDR_SDRAM_32Mx64_DDR_DM
PORT DDR_DQS = fpga_0_DDR_SDRAM_32Mx64_DDR_DQS
PORT DDR_DQ = fpga_0_DDR_SDRAM_32Mx64_DDR_DQ
PORT DDR_Clk = fpga_0_DDR_SDRAM_32Mx64_DDR_Clk & ddr_clk_feedback_out_s
PORT DDR_Clkn = fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn & 0b0
PORT Clk90_in = clk_90_s
PORT Clk90_in_n = clk_90_n_s
PORT OPB_Clk_n = sys_clk_n_s
PORT DDR_Clk90_in = ddr_clk_90_s
PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END