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[microblaze-uclinux] mb + uclinux on V4LC development board

Hi all,
         i am trying to build a uclinux + microblaze system on Virtex 4 LC development board and i have also read http://www.itee.uq.edu.au/~wu/downloads/uClinux_ready_Microblaze_design.pdf. I am using uclinux 1.00.a since v4lc evaluation board does not have any flash. I could generate the libraries but encouter this error when generating the netlist :
 
Running XST synthesis ...

INFO:MDT - The following instances are synthesized with XST. The MPD option

IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST

synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.

microblaze_0_wrapper (microblaze_0) - C:\test\system.mhs:56 - Running XST

synthesis

mb_opb_wrapper (mb_opb) - C:\test\system.mhs:89 - Running XST synthesis

debug_module_wrapper (debug_module) - C:\test\system.mhs:97 - Running XST

synthesis

ERROR:MDT - HDL synthesis failed!

INFO:MDT - Refer to C:\test\synthesis\debug_module_wrapper_xst.srp for details

ERROR:MDT - platgen failed with errors!

make: *** [implementation/microblaze_0_wrapper.ngc] Error 2

Done.

 

The following is the debug_module_wrapper_xst.srp file :

 

Release 7.1.02i - xst H.41

Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.

--> 

TABLE OF CONTENTS

1) Synthesis Options Summary

2) HDL Compilation

3) HDL Analysis

4) HDL Synthesis

5) Advanced HDL Synthesis

5.1) HDL Synthesis Report

6) Low Level Synthesis

7) Final Report

7.1) Device utilization summary

7.2) TIMING REPORT

 

=========================================================================

* Synthesis Options Summary *

=========================================================================

---- Source Parameters

Input Format : MIXED

Input File Name : "debug_module_wrapper_xst.prj"

---- Target Parameters

Target Device : xc4vlx25sf363-10

Output File Name : "../implementation/debug_module_wrapper/debug_module_wrapper.ngc"

---- Source Options

Top Module Name : debug_module_wrapper

---- Target Options

Add IO Buffers : NO

---- General Options

Optimization Goal : speed

RTL Output : YES

Hierarchy Separator : /

---- Other Options

Cores Search Directories : {../implementation/debug_module_wrapper}

=========================================================================

WARNING:Xst:29 - Optimization Effort not specified

The following parameters have been added:

Optimization Effort : 1

=========================================================================

=========================================================================

* HDL Compilation *

=========================================================================

Compiling vhdl file "C:/test/pcores/opb_mdm_v2_01_a/hdl/vhdl/srl_fifo.vhd" in Library opb_mdm_v2_01_a.

Entity <SRL_FIFO> compiled.

Entity <SRL_FIFO> (Architecture <IMP>) compiled.

Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_c/hdl/vhdl/pselect.vhd" in Library proc_common_v1_00_c.

Entity <pselect> compiled.

Entity <pselect> (Architecture <imp>) compiled.

Compiling vhdl file "C:/test/pcores/opb_mdm_v2_01_a/hdl/vhdl/jtag_control.vhd" in Library opb_mdm_v2_01_a.

Entity <JTAG_CONTROL> compiled.

Entity <JTAG_CONTROL> (Architecture <IMP>) compiled.

Compiling vhdl file "C:/test/pcores/opb_mdm_v2_01_a/hdl/vhdl/bscan_virtex.vhd" in Library opb_mdm_v2_01_a.

Entity <BSCAN_VIRTEX> compiled.

Entity <BSCAN_VIRTEX> (Architecture <Behavioral>) compiled.

Compiling vhdl file "C:/test/pcores/opb_mdm_v2_01_a/hdl/vhdl/mdm_core.vhd" in Library opb_mdm_v2_01_a.

Entity <MDM_Core> compiled.

Entity <MDM_Core> (Architecture <IMP>) compiled.

Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_c/hdl/vhdl/family.vhd" in Library proc_common_v1_00_c.

Package <family> compiled.

Package body <family> compiled.

Compiling vhdl file "C:/test/pcores/opb_mdm_v2_01_a/hdl/vhdl/mdm.vhd" in Library opb_mdm_v2_01_a.

Entity <OPB_MDM> compiled.

Entity <OPB_MDM> (Architecture <IMP>) compiled.

Compiling vhdl file "C:/test/synthesis/../hdl/debug_module_wrapper.vhd" in Library work.

Entity <debug_module_wrapper> compiled.

Entity <debug_module_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================

* HDL Analysis *

=========================================================================

Analyzing Entity <debug_module_wrapper> (Architecture <STRUCTURE>).

Set user-defined property "X_CORE_INFO = opb_mdm_v2_01_a" for unit <debug_module_wrapper>.

Instantiating component <opb_mdm> from Library <opb_mdm_v2_01_a>.

Entity <debug_module_wrapper> analyzed. Unit <debug_module_wrapper> generated.

Analyzing generic Entity <opb_mdm> (Architecture <imp>).

C_BASEADDR = <u>01000001010000000000000000000000

C_HIGHADDR = <u>01000001010000001111111111111111

C_OPB_DWIDTH = 32

C_OPB_AWIDTH = 32

C_FAMILY = "virtex4"

C_MB_DBG_PORTS = 1

C_USE_UART = 1

C_UART_WIDTH = 0

C_WRITE_FSL_PORTS = 1

Set user-defined property "PERIOD = 80" for signal <drck_i>.

WARNING:Xst:753 - "C:/test/pcores/opb_mdm_v2_01_a/hdl/vhdl/mdm.vhd" line 511: Unconnected output port 'jtag_clk' of component 'MDM_Core'.

WARNING:Xst:753 - "C:/test/pcores/opb_mdm_v2_01_a/hdl/vhdl/mdm.vhd" line 511: Unconnected output port 'trig' of component 'MDM_Core'.

WARNING:Xst:753 - "C:/test/pcores/opb_mdm_v2_01_a/hdl/vhdl/mdm.vhd" line 511: Unconnected output port 'data' of component 'MDM_Core'.

Entity <opb_mdm> analyzed. Unit <opb_mdm> generated.

Analyzing generic Entity <MDM_Core> (Architecture <imp>).

C_BASEADDR = <u>01000001010000000000000000000000

C_HIGHADDR = <u>01000001010000001111111111111111

C_MB_DBG_PORTS = 1

C_USE_UART = 1

C_UART_WIDTH = 0

C_USE_FSL = 1

C_FSL_DATA_SIZE = 32

WARNING:Xst:1994 - "C:/test/pcores/opb_mdm_v2_01_a/hdl/vhdl/mdm_core.vhd" line 353: Null range in type of signal <rx_Data>.

Instantiating component <pselect> from Library <proc_common_v1_00_c>.

WARNING:Xst:1995 - "C:/test/pcores/opb_mdm_v2_01_a/hdl/vhdl/mdm_core.vhd" line 502: Use of null array on signal <rx_Data> is not supported.

FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13.276.1 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com

I have googled the error to no avail. Can someone give me some advice on how to resolve this ? 

Thanks for your time.

Regards,

Zijia


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