RE: [microblaze-uclinux] Microblaze caches latencies

["Goran Bilski" <goran.bilski@xxxxxxxxxx>]

Hi,

It takes 2 clock cycles on cache hits on the data side.
The instruction side is using overlapped address and data phases so even if the access takes 2 clock cycles, MicroBlaze can fetch one new instruction every clock cycle.

Göran

-----Original Message-----
From: owner-microblaze-uclinux@itee.uq.edu.au [mailto:owner-microblaze-uclinux@itee.uq.edu.au] On Behalf Of Pavel Ivanchenko
Sent: Saturday, September 03, 2005 21:35
To: microblaze-uclinux@itee.uq.edu.au
Subject: [microblaze-uclinux] Microblaze caches latencies

Hi.
How many ticks of processor core need for execute command (or read data) 
from cache?
Earlier I'm where that has read 2 tick of processor core, but now dont find 
info about cache latencies. 

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