RE: [microblaze-uclinux] why such idiv latency of 34 cycles?

["Goran Bilski" <goran.bilski@xxxxxxxxxx>]

Hi,

There is a nice article on Xilinx website in the techexclusive section.
It describes on how to accelerate SW function by using the FSL interface on Microblaze.

http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=3&sTechX_ID=rg_root_evil

Göran

-----Original Message-----
From: owner-microblaze-uclinux@itee.uq.edu.au [mailto:owner-microblaze-uclinux@itee.uq.edu.au] On Behalf Of Brettschneider Falk
Sent: Friday, August 26, 2005 11:13
To: 'microblaze-uclinux@itee.uq.edu.au'
Subject: RE: [microblaze-uclinux] why such idiv latency of 34 cycles?

Thanks, understood now. Yes, that's always an option, but some things here
are solved in a common C programm running on µLinux. First developed on a PC
and than compiled for µLinux. Actually, they aren't schedulled for a port to
a real FPGA module. That's why it would be good, if the operator / of the C
progam in µLinux was faster, you know.

Cheers
F@lk


Göran Bilski wrote:
> 
> Try to grab as high level function as possible to improve the 
> performance of your application.
> 
> Don't add a MAC instruction with some saturation.
> Try to take sections that include loops to be a magnitude 
> better performance.
> When I accelerated a JPEG decoder, I place the idct function 
> in HW and just send the parameter from MicroBlaze over FSL to 
> the function.
> 
> Göran

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