RE: [microblaze-uclinux] Microblaze caches latencies

["Goran Bilski" <goran.bilski@xxxxxxxxxx>]

Hi Pavel,

That will not work.

MicroBlaze is a single-clock synchronous design. 
Everything has to be clocked with the same clock source.

Also the BRAM clk-to-out delay prohibit a faster clock, you would then need to add a flipflop to remove the critical path and then the whole purpose of double clock the cache has been wasted.

Göran

-----Original Message-----
From: owner-microblaze-uclinux@itee.uq.edu.au [mailto:owner-microblaze-uclinux@itee.uq.edu.au] On Behalf Of Pavel Ivanchenko
Sent: Monday, September 05, 2005 22:23
To: microblaze-uclinux@itee.uq.edu.au
Subject: Re: [microblaze-uclinux] Microblaze caches latencies

Sorry, error in previous mesage, I wanted say:

 I'm try connect double tck to clock input of  Icache module, no effects :(

----- Original Message ----- 
From: "Pavel Ivanchenko" <pi-home@udm.net>
To: <microblaze-uclinux@itee.uq.edu.au>
Sent: Monday, September 05, 2005 9:09 PM
Subject: Re: [microblaze-uclinux] Microblaze caches latencies


> Hi.
>
> Interesting, exist possibility way to up performace of chaches.
>
> I'm try connect to clock input of  Icache module, no effects :(
>
> ----- Original Message ----- 
>
> From: "Goran Bilski" <goran.bilski@xilinx.com>
> To: <microblaze-uclinux@itee.uq.edu.au>
> Sent: Monday, September 05, 2005 11:31 AM
> Subject: RE: [microblaze-uclinux] Microblaze caches latencies
>
>
>> Hi,
>>
>> It takes 2 clock cycles on cache hits on the data side.
>> The instruction side is using overlapped address and data phases so even 
>> if the access takes 2 clock cycles, MicroBlaze can fetch one new 
>> instruction every clock cycle.
>>
>> Göran
>>
>> -----Original Message-----
>> From: owner-microblaze-uclinux@itee.uq.edu.au 
>> [mailto:owner-microblaze-uclinux@itee.uq.edu.au] On Behalf Of Pavel 
>> Ivanchenko
>> Sent: Saturday, September 03, 2005 21:35
>> To: microblaze-uclinux@itee.uq.edu.au
>> Subject: [microblaze-uclinux] Microblaze caches latencies
>>
>> Hi.
>> How many ticks of processor core need for execute command (or read data)
>> from cache?
>> Earlier I'm where that has read 2 tick of processor core, but now dont 
>> find
>> info about cache latencies.
>>
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>>
>>
>>
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