RE: [microblaze-uclinux] why such idiv latency of 34 cycles?

[Brettschneider Falk <fbrettschneider@xxxxxxxxxxxxxxxxx>]

Hi Göran,

thanks very much. I'll keep you cool links in mind. It's good to know that
it's possible and where to find the manuals for it, to speed up certain SW
bottlenecks this way.
I think it'll become an option when the pressure increases to make things
faster.

Cheers
F@lk

> -----Original Message-----
> From: owner-microblaze-uclinux@itee.uq.edu.au
> [mailto:owner-microblaze-uclinux@itee.uq.edu.au]On Behalf Of Goran
> Bilski
> 
> There is a nice article on Xilinx website in the 
> techexclusive section.
> It describes on how to accelerate SW function by using the 
> FSL interface on Microblaze.
> 
>
http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondar
yNavPick=&category=&iLanguageID=1&multPartNum=3&sTechX_ID=rg_root_evil
> 
> Göran

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