Hello Folks, I have a question involving the final running clock frequency on the Microblaze. I am using a pretty strange platform, a Nu-Horizons S3-400. It has a 20 MHz crystal oscillator as its input clock. In EDK when I set up my hardware in BSB, one of the first things it asks is the Reference Clock Frequency. This pulldown has no option for a 20 Mhz clock input, in fact 40 MHz is as low as it goes. Is this a design lmiting factor? Could this mean that the microblaze thinks its taking its 50 MHz clock input to get its 100 MHz core clock, that it really is getting a 40 MHz clock? I will include my MSS and MHS files if they are of any concequence. Thanks, Andy _________________________________________________________________ Express yourself instantly with MSN Messenger! Download today - it's FREE! http://messenger.msn.click-url.com/go/onm00200471ave/direct/01/
Attachment:
system.mhs
Description: Binary data
Attachment:
system.mss
Description: Binary data
/******************************************************************* * * CAUTION: This file is automatically generated by libgen. * Version: Xilinx EDK 7.1.2 EDK_H.12.5.1 * DO NOT EDIT. * * Copyright (c) 2005 Xilinx, Inc. All rights reserved. * * Description: Driver parameters * *******************************************************************/ #define STDIN_BASEADDRESS 0x40600000 #define STDOUT_BASEADDRESS 0x40600000 /******************************************************************/ #define XPAR_DLMB_CNTLR_BASEADDR 0x00000000 #define XPAR_DLMB_CNTLR_HIGHADDR 0x00001FFF #define XPAR_ILMB_CNTLR_BASEADDR 0x00000000 #define XPAR_ILMB_CNTLR_HIGHADDR 0x00001FFF /******************************************************************/ #define XPAR_XUARTLITE_NUM_INSTANCES 2 #define XPAR_DEBUG_MODULE_BASEADDR 0x41400000 #define XPAR_DEBUG_MODULE_HIGHADDR 0x4140FFFF #define XPAR_DEBUG_MODULE_DEVICE_ID 0 #define XPAR_DEBUG_MODULE_BAUDRATE 0 #define XPAR_DEBUG_MODULE_USE_PARITY 0 #define XPAR_DEBUG_MODULE_ODD_PARITY 0 #define XPAR_DEBUG_MODULE_DATA_BITS 0 #define XPAR_RS232_BASEADDR 0x40600000 #define XPAR_RS232_HIGHADDR 0x4060FFFF #define XPAR_RS232_DEVICE_ID 1 #define XPAR_RS232_BAUDRATE 9600 #define XPAR_RS232_USE_PARITY 0 #define XPAR_RS232_ODD_PARITY 0 #define XPAR_RS232_DATA_BITS 8 /******************************************************************/ #define XPAR_XGPIO_NUM_INSTANCES 3 #define XPAR_LEDS_8BIT_BASEADDR 0x40020000 #define XPAR_LEDS_8BIT_HIGHADDR 0x4002FFFF #define XPAR_LEDS_8BIT_DEVICE_ID 0 #define XPAR_LEDS_8BIT_INTERRUPT_PRESENT 0 #define XPAR_LEDS_8BIT_IS_DUAL 0 #define XPAR_PUSH_BUTTONS_2BIT_BASEADDR 0x40000000 #define XPAR_PUSH_BUTTONS_2BIT_HIGHADDR 0x4000FFFF #define XPAR_PUSH_BUTTONS_2BIT_DEVICE_ID 1 #define XPAR_PUSH_BUTTONS_2BIT_INTERRUPT_PRESENT 0 #define XPAR_PUSH_BUTTONS_2BIT_IS_DUAL 0 #define XPAR_LCDDISPLAY_12BIT_BASEADDR 0x40040000 #define XPAR_LCDDISPLAY_12BIT_HIGHADDR 0x4004FFFF #define XPAR_LCDDISPLAY_12BIT_DEVICE_ID 2 #define XPAR_LCDDISPLAY_12BIT_INTERRUPT_PRESENT 0 #define XPAR_LCDDISPLAY_12BIT_IS_DUAL 0 /******************************************************************/ #define XPAR_XSPI_NUM_INSTANCES 2 #define XPAR_ADC_BASEADDR 0x40A20000 #define XPAR_ADC_HIGHADDR 0x40A2FFFF #define XPAR_ADC_DEVICE_ID 0 #define XPAR_ADC_FIFO_EXIST 1 #define XPAR_ADC_SPI_SLAVE_ONLY 0 #define XPAR_ADC_NUM_SS_BITS 1 #define XPAR_DAC_BASEADDR 0x40A00000 #define XPAR_DAC_HIGHADDR 0x40A0FFFF #define XPAR_DAC_DEVICE_ID 1 #define XPAR_DAC_FIFO_EXIST 1 #define XPAR_DAC_SPI_SLAVE_ONLY 0 #define XPAR_DAC_NUM_SS_BITS 1 /******************************************************************/ #define XPAR_SDRAM_4MX16_MEM0_BASEADDR 0x20800000 #define XPAR_SDRAM_4MX16_MEM0_HIGHADDR 0x20FFFFFF /******************************************************************/ #define XPAR_XTMRCTR_NUM_INSTANCES 1 #define XPAR_OPB_TIMER_1_BASEADDR 0x41C00000 #define XPAR_OPB_TIMER_1_HIGHADDR 0x41C0FFFF #define XPAR_OPB_TIMER_1_DEVICE_ID 0 /******************************************************************/ #define XPAR_INTC_MAX_NUM_INTR_INPUTS 3 #define XPAR_XINTC_HAS_IPR 1 #define XPAR_XINTC_USE_DCR 0 #define XPAR_XINTC_NUM_INSTANCES 1 #define XPAR_OPB_INTC_0_BASEADDR 0x41200000 #define XPAR_OPB_INTC_0_HIGHADDR 0x4120FFFF #define XPAR_OPB_INTC_0_DEVICE_ID 0 #define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000000 /******************************************************************/ #define XPAR_INTC_SINGLE_BASEADDR 0x41200000 #define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF #define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID #define XPAR_OPB_TIMER_1_INTERRUPT_MASK 0X000001 #define XPAR_OPB_INTC_0_OPB_TIMER_1_INTERRUPT_INTR 0 #define XPAR_DAC_IP2INTC_IRPT_MASK 0X000002 #define XPAR_OPB_INTC_0_DAC_IP2INTC_IRPT_INTR 1 #define XPAR_ADC_IP2INTC_IRPT_MASK 0X000004 #define XPAR_OPB_INTC_0_ADC_IP2INTC_IRPT_INTR 2 /******************************************************************/ #define XPAR_CPU_CORE_CLOCK_FREQ_HZ 100000000 /******************************************************************/