[microblaze-uclinux] Problem with ethernet (no PHY detected)

[Arnaud Lagger <arnaud.lagger@xxxxxxx>]

Hello,

I have a problem regarding the configuration of my ethernet peripheric 
for my board.

Here are the steps that I did to integrate opb_ethernet:
1) Took the uClinux_auto platform.
2) Add the opb_ethernet in "add cores" in EDK
3) Put ethernet in slave mode
4) Generate the addresses
5) Add all the signals in the "ports tab", except "Freeze". Made 
external all the PHY signals.
Connected the interrupt signal to the interrupt controller (just after 
the timer interrupt).
Additionally, I connected another interrupt signal (phy_mii_int_n) which 
goes through a misc_logic.
6) Customized ethernet whith those parameters values:
  PARAMETER C_DMA_PRESENT = 1
  PARAMETER C_OPB_CLK_PERIOD_PS = 15000
  PARAMETER C_IPIF_RDFIFO_DEPTH = 16384
  PARAMETER C_IPIF_WRFIFO_DEPTH = 16384
  PARAMETER C_RESET_PRESENT = 0
  PARAMETER C_DEV_BLK_ID = 0

7) Compiled the uClinux kernel with networking support and ethernet driver.

Here is the message when I boot uClinux:

eth0: using fifo mode.
eth0: No PHY detected.  Assuming a PHY at address 0.
eth0: Xilinx EMAC #0 at 0xFFFF8000 mapped to 0xFFFF8000, irq=1
eth0: id 0.0a; block id 0, type 0

Any idea?

Thanks,

Arnaud Lagger

----

Here is the part of my .mhs concerning ethernet:

BEGIN opb_ethernet
  PARAMETER INSTANCE = enet
  PARAMETER HW_VER = 1.02.a
  PARAMETER C_DMA_PRESENT = 1
  PARAMETER C_OPB_CLK_PERIOD_PS = 15000
  PARAMETER C_IPIF_RDFIFO_DEPTH = 16384
  PARAMETER C_IPIF_WRFIFO_DEPTH = 16384
  PARAMETER C_RESET_PRESENT = 0
  PARAMETER C_BASEADDR = 0xffff8000
  PARAMETER C_HIGHADDR = 0xffffbfff
  PARAMETER C_DEV_BLK_ID = 0
  BUS_INTERFACE SOPB = mb_opb
  PORT PHY_crs = enet_PHY_crs
  PORT PHY_dv = enet_PHY_dv
  PORT PHY_rx_clk = enet_PHY_rx_clk
  PORT PHY_tx_clk = enet_PHY_tx_clk
  PORT PHY_col = enet_PHY_col
  PORT PHY_rx_data = enet_PHY_rx_data
  PORT PHY_rx_er = enet_PHY_rx_er
  PORT IP2INTC_Irpt = enet_IP2INTC_Irpt
  PORT emac_intrpts = enet_emac_intrpts
  PORT PHY_Mii_data = enet_PHY_Mii_data
  PORT PHY_rst_n = net_vcc
  PORT PHY_tx_data = enet_PHY_tx_data
  PORT PHY_tx_er = enet_PHY_tx_er
  PORT PHY_rx_en = enet_PHY_rx_en
  PORT PHY_tx_en = enet_PHY_tx_en
  PORT PHY_Mii_clk = enet_PHY_Mii_clk
  PORT OPB_Clk = sys_clk
  PORT Freeze = net_gnd
END

----

Here is my ucf:

# Ethernet
NET "enet_PHY_rx_data<0>" LOC = "A10";
NET "enet_PHY_rx_data<1>" LOC = "B10";
NET "enet_PHY_rx_data<2>" LOC = "C10";
NET "enet_PHY_rx_data<3>" LOC = "D10";
NET "enet_PHY_rx_data<0>" NODELAY;
NET "enet_PHY_rx_data<1>" NODELAY;
NET "enet_PHY_rx_data<2>" NODELAY;
NET "enet_PHY_rx_data<3>" NODELAY;

NET "enet_PHY_tx_data<0>" LOC = "D7";
NET "enet_PHY_tx_data<1>" LOC = "E7";
NET "enet_PHY_tx_data<2>" LOC = "A8";
NET "enet_PHY_tx_data<3>" LOC = "B8";

NET "enet_PHY_dv" LOC = "E10";
NET "enet_PHY_dv" NODELAY;
NET "enet_PHY_rx_er" LOC = "A11";
NET "enet_PHY_rx_er" NODELAY;
NET "enet_PHY_tx_en" LOC = "C8";
# Not needed for etlite
NET "enet_PHY_tx_er" LOC = "D8";

NET "enet_PHY_tx_clk" LOC = "E20";
NET "enet_PHY_rx_clk" LOC = "F22";
NET "enet_PHY_tx_clk" TNM_NET = "TXCLK_GRP";
NET "enet_PHY_rx_clk" TNM_NET = "RXCLK_GRP";
TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;
TIMESPEC "TSRXIN"  = FROM "PADS" TO "RXCLK_GRP" 6 ns;
NET "enet_PHY_tx_clk" MAXSKEW = 2.0 ns;
NET "enet_PHY_rx_clk" MAXSKEW = 2.0 ns;
NET "enet_PHY_tx_clk" PERIOD = 40 ns HIGH 14 ns;
NET "enet_PHY_rx_clk" PERIOD = 40 ns HIGH 14 ns;

NET "enet_PHY_crs" LOC = "B7";
NET "enet_PHY_crs" NODELAY;
NET "enet_PHY_col" LOC = "C7";
NET "enet_PHY_col" NODELAY;
#NET "enet_PHY_rst_n" LOC = "B18";
#NET "enet_PHY_rst_n" TIG;

#not needed for etlite
NET "enet_PHY_Mii_data" LOC = "B17";
NET "enet_PHY_Mii_clk" LOC = "C17";
NET "misc_logic_0_phy_mii_int_n" LOC = "C18";
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