[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [microblaze-uclinux] Jtag Debug
Greg - Just curious: How did you figure out the correct phase
alignment. In general how do you go about debugging any DDR issues?
Excellent debugging btw!
On 10/28/05, Greg A Martin <gregmartin@xxxxxxxxxx> wrote:
Just a note on the mch_opb_ddr controller, I am running 66Mhz/133Mhz with
16-bit DDR and was seeing problems similar to what John reported below. At
66 MHz the DQS window is pretty slim and if the feedback clock is out of
phase enough, the controller misses the DQS for read data causing reads to
not be acknowledged. This presents itself as a stalled pipeline message in
the XDM debugger and a hung system. The behavior varies from route to route
unless you lock down the DCM's and global clock buffer positions. Once I
locked down the positions and determined the correct DCM phase alignment, I
have been getting much more consistent behavior. Additional info, I am
running on a Spartan3e 500 device that is virtually full. The behavior
manifested itself as the design got closer and closer to 100% utilization.
Also, since I am cheap, I chose not to use the external feedback for the
DDR, instead using DCM phase adjustment to delay the feedback clock
appropriately. (pins are just to valuable to waste on phase delay when the
DCM's can do it anyhow).