-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi Paul,I did not use the openssl hardware accelerator interface in this case. I profiled the code on the powerPC arch to get an idea of where all the time was being spent. In the case of AES, 80% of the CPU time was being consumed in a specific function, so I just moved the bulk of the processing from that into hardware.
It's tough to run direct comparisons on the uClib platform because profiling doesn't work (I guess it was removed?), otherwise I could a line by line comparison. I'm using Handel-C to create the hardware, and the language is cycle based, so I could do a direct time comparison neglecting overhead (IE one Handel-C assignment statement takes 1 clock cycle, all other statements are 'free').
At this stage, the hardware is working correctly (yay!), so now I need to examine the possibility of reducing the amount of data being sent over the link. I will probably have to do some stream processing to reduce the number of transactions, but hopefully I can reduce the number of reads/writes down to 2 write, and 2 read per 64 bits of data.
Claudio,Let me give the counters a shot. The current depth of the FIFO is 16, but the only time there is a lot of data (greater than the depth of the fifo) being sent is when the encryption algorithm initially sets up. The hardware processes so quickly that the time spent waiting for the 8 reads shouldn't be too high. I've put the counters into the FSL driver and will report back.
Now that I also know my design fits on my chip, I have re-enabled the on-chip cache (32kB I / 32kB D) and received a huge overall speed up (but software is still faster overall).
Hardware: real 0m 26.66s user 0m 3.97s sys 0m 13.93s Software: real 0m 9.48s user 0m 6.34s sys 0m 3.14s - ------------------------------------- Jonathan Jung On Jan 3, 2006, at 7:32 AM, Paul Hartke wrote:
Sounds like a cool project. Are you using the opensll engine interface to interface with your module? Have you run standalone synthetic benchmarks to determine the amount of speedup to expect? 4 FSL writes and 8 FSL readsfor every 64 bits of data to be encrypted isn't so efficient. Paul Quoting Jonathan Jung <jwjung@xxxxxxxxxxxxx>:-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi List, I've had good success implementing a hardware accelerated version of Openssl on my Virtex II Pro FPGA via uClinux. However, I'm wondering if anybody has experience with the amount of overhead involved FSL reading/writing. For example, encrypting a 700KB file in software takes (using AES): real 2m 9.96s user 1m 33.98s sys 0m 33.29s (file read/writes) Encrypting the same 700 KB file with software/hardware takes: real 3m 23.51s user 0m 10.40s sys 1m 56.57s (file read/writes, FSL read/write) As you can see, software version consumes 1m 33 s of CPU time running the openssl code. The hardware/software combo takes only 10 seconds of time executing the openssl code, but requires 1 minute and 56 seconds of overhead in unrelated system calls, I'm sure is because of the reading and writing to the FSL. Each 64 bits of data encrypted requires 4 FSL writes, and 8 FSL Reads. The initial one time setup requires 60 FSL writes. The hardware is quite fast, running at 100 Mhz, and requires only about 30 cycles to process the data. The profiler in uClib isn't active anymore, so I can't use that to do a line by line check for the time it takes for each write, but a best estimate is it takes almost a minute and half to do all those reads and writes. Am I doing something funny, or is that just the amount of overhead required? I'm only doing the initial drive init once throughout the whole process. The FSL driver doesn't look like it's doing too many crazy things to write to the FSL, so I wouldn't think that would be the time consumer. Any FSL related performance comments are welcome! Thanks again to John for the excellent driver. Jonathan -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.1 (Darwin) iD8DBQFDuiSK4kOt3FHegqgRAtNvAJ9ZLn3RkaQJmvPSZFCYgGmE0MERnwCeKC+m aTBhl1P+Uu3gKIf2ZEs2c68= =M2Dp -----END PGP SIGNATURE-----___________________________ microblaze-uclinux mailing list microblaze-uclinux@xxxxxxxxxxxxxxProject Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze- uclinux Mailing List Archive : http://www.itee.uq.edu.au/~listarch/ microblaze-uclinux/
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