|
Hi,
I use Spartan3-200 (12 BRAMs) to MicroBlaze
uClinux system (EDK7.1.02, ISE7.1.03).
In documentation say:
E.g. assuming a configuration of C_ICACHE_BASEADDR=
0x00300000, >C_ICACHE_HIGHADDR=0x0030ffff, and C_CACHE_BYTE_SIZE=4096; the
cacheable byte address range is 16 bits, and the cache byte address range is 12
bits (i.e. a 10 bit cache word address), thus the required address tag is:
16-12=4 bits.
The total number of primitives required in the example above is: 2 RAMB16 for storing the 1024 instructions, and 1 RAMB16 for tag and status (4 bits of tag + 1 valid bit + 1 lock bit), i.e. a total of 3 RAMB16 primitives. My SDRAM range 0x40000000 -
0x41ffffff.
So, if I include 4k ICACHE it use 3 BRAM, if I
include any size DCACHE (from 2k to 8k) in any case it use 6 BRAM.
In case with Virtex or big Spartan it not
important, but for my system it very important.
Pavel.
|