Also, according to John, the bug could cause the MB to lock up by the XCL. However, in my case, the DDR does not hold the data and has nothing to do with XCL. Actually, I'd like to use this MCH_DDR for shared memory access. There is a high-speed fibre peripheral, and I want the data to be stored directly to the DDR RAM instead of via any bus like OPB. uCLinux/MB serves as a low speed monitor, hence the MCH_DDR is connected to MB via OPB instead of any XCL. Attached the MHS file. At the moment the XCL interface on the MCH_DDR does not do anything, although it connects to the icache port. All the tested accessing is through the OPB. Cheers David -----Original Message----- From: owner-microblaze-uclinux@xxxxxxxxxxxxxx [mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] On Behalf Of Paul Hartke Sent: 12 January 2006 19:26 To: microblaze-uclinux@xxxxxxxxxxxxxx; Deli Geng (David) Cc: microblaze-uclinux@xxxxxxxxxxxxxx Subject: Re: [microblaze-uclinux] mch_ddr on XUP V2P board See John's post on this topic: http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/archive/2005/10/msg00 206.html I haven't seen a patch from Xilinx for the mch_opb_ddr controller issues. Paul Quoting "Deli Geng (David)" <deli.geng@xxxxxxxxxxxx>: > > Hi, there, > > Has anyone successfully configured to use the mch_ddr on Xilinx XUP V2P > board? I try many times, but the memory test always fails. > > Thanks > > David > ___________________________ microblaze-uclinux mailing list microblaze-uclinux@xxxxxxxxxxxxxx Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
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